Performance-aware and reliability-aware data placement for n-level heterogeneous memory systems

• US 10,365,996 B2
• Filed: 10/21/2016
• Issued: 07/30/2019
• Est. Priority Date: 03/24/2016
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gupta, Manish, Roberts, David A., Meswani, Mitesh R., Sridharan, Vilas, Raasch, Steven, Lowell, Daniel I.
• Primary Examiner(s): Talukdar, Arvind
• Application Number:
  US15/331,270
• Publication Number:
  US 20170277441A1
• Time in Patent Office: 1,012 Days
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00

Abstract

Techniques for selecting one of a plurality of heterogeneous memory units for placement of blocks of data (e.g., memory pages), based on both reliability and performance, are disclosed. A “cost” for each data block/memory unit combination is determined, based on the frequency of access of the data block, the latency of the memory unit, and, optionally, an architectural vulnerability factor (which represents the level of exposure of a particular memory data value to memory faults such as bit flips). A memory unit is selected for the data block for which the determined cost is the lowest, out of all memory units considered, and the data block is placed into that memory unit.

Claims

1. A method for identifying one memory unit, of a plurality of memory units, for storage of a block of data, the method comprising:

generating failure rates for the plurality of memory units by;

performing a plurality of fault simulations by performing a series of fault simulation iterations, each fault simulation iteration including simulating fault occurrences and error correction, and determining whether error correcting code is not able to correct at least one error,

determining a time-to-failure value for each fault simulation by determining the number of fault simulation iterations that occur before an error could not be corrected and an amount of time representative of each fault simulation iteration, and

determining the failure rates based on the time-to-failure values;

determining, for the block of data, a plurality of costs, each cost corresponding to a different memory unit of the plurality of memory units, based on a comparison of the determined failure rates of the memory units to a combination of hotness values that indicate frequency of access of the block of data and latencies of the memory units;

selecting a cost of the plurality of costs, the selected cost being either the highest of the plurality of costs or the lowest of the plurality of costs; and

migrating the block of data to a memory unit of the plurality of memory units that is associated with the selected cost.

2. The method of claim 1, wherein the migrating comprises:

responsive to determining that the block of data is not stored in the memory unit that is associated with the selected cost, migrating the block of memory to the memory unit that is associated with the selected cost.

3. The method of claim 1, wherein:

the determining, selecting, and migrating steps are performed in response to one or more of a periodic time span elapsing, receipt of one or more reliability information updates for one or more memory units of the plurality of memory units, or receipt of a frequency of access information update for the block of data.

4. The method of claim 1, wherein:

determining the plurality of costs is further based on an architectural vulnerability factor for the block of data, the architectural vulnerability factor comprising an indication of vulnerability of data in the block of data to memory faults.

5. The method of claim 1, wherein:

determining the plurality of costs comprises evaluating the expression;

Cost_Mi=α

*FIT_Mi*AVF[data_block]−

(1−

α

)*Hotness[data_block]/latency_Mi,

where;

Cost_Mi comprises the cost of a memory unit M_i;

FIT_Mi comprises a failure-in-time rate of the memory unit M_i;

AVF[data_block] comprises an architectural vulnerability factor for the block of data;

Hotness[data_block] comprises an indication of frequency of access of the block of data;

Latency comprises latency of access of the memory unit M_i; and

α

comprises a tunable trade-off factor that indicates relative importance of performance and reliability.

6. The method of claim 5, wherein selecting the cost of the plurality of costs comprises selecting the lowest cost of the plurality of costs.

7. The method of claim 5, wherein a is associated with a specific computer process.

8. A computer system for identifying one memory unit, of a plurality of memory units, for storage of a block of data, the computer system comprising:

a processing unit;

a plurality of memory units coupled to the processing unit;

a failure-in-time rate logger configured to generate failure rates for the plurality of memory units by;

performing a plurality of fault simulations by performing a series of fault simulation iterations, each fault simulation iteration including simulating fault occurrences and error correction, and determining whether error correcting code is not able to correct at least one error,

determining a time-to-failure value for each fault simulation by determining the number of fault simulation iterations that occur before an error could not be corrected and an amount of time representative of each fault simulation iteration, and

determining the failure rates based on the time-to-failure values;

a page placement module configured to;

determine, for the block of data, a plurality of costs, each cost corresponding to a different memory unit of the plurality of memory units, based on a comparison of the determined failure rates of the memory units to a combination of hotness values that indicate frequency of access of the block of data and latencies of the memory units,

select a cost, of the plurality of costs, the selected cost being either the highest of the plurality of costs or the lowest of the plurality of costs, and

migrate the block of data to a memory unit of the plurality of memory units that is associated with the selected cost.

9. The computer system of claim 8, wherein the page placement module is configured to migrate the block of data to the memory unit of the plurality of memory units that is associated with the selected cost by:

responsive to determining whether the block of data is stored in the memory unit that is associated with the selected cost, migrating the block of memory unit to the memory unit that is associated with the selected cost.

10. The computer system of claim 8, wherein the page placement module is configured to determine the plurality of costs, select the cost, and migrate the block of data in response to one or more of a periodic time span elapsing, receipt of one or more reliability information updates for one or more memory units of the plurality of memory units, or receipt of a frequency of access information update for the block of data.

11. The computer system of claim 8, wherein the page placement module is configured to determine the plurality of costs further based on an architectural vulnerability factor for the block of data, the architectural vulnerability factor comprising an indication of vulnerability of data in the block of data to memory faults.

12. The computer system of claim 8, wherein the page placement module is configured to determine the plurality of costs by evaluating the expression:

Cost_Mi=α

*FIT_Mi*AVF[data_block]−

(1−

α

)*Hotness[data_block]/latency_Mi,

where;

Cost_Mi comprises the cost of a memory unit M_i;

FIT_Mi comprises a failure-in-time rate of the memory unit M_i;

AVF[data_block] comprises an architectural vulnerability factor for the block of data;

Hotness[data_block] comprises an indication of frequency of access of the block of data;

Latency comprises latency of access of the memory unit M_i; and

α

comprises a tunable trade-off factor that indicates relative importance of performance and reliability.

13. The computer system of claim 12, wherein the page placement module is configured to select the cost of the plurality of costs by selecting the lowest cost of the plurality of costs.

14. The computer system of claim 12, wherein a is associated with a specific computer process.

15. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to identify one memory unit, of a plurality of memory units, for storage of a block of data by performing a method comprising:

generating failure rates for the plurality of memory units by;

performing a plurality of fault simulations by performing a series of fault simulation iterations, each fault simulation iteration including simulating fault occurrences and error correction, and determining whether error correcting code is not able to correct at least one error,

determining a time-to-failure value for each fault simulation by determining the number of fault simulation iterations that occur before an error could not be corrected and an amount of time representative of each fault simulation iteration, and

determining the failure rates based on the time-to-failure values;

determining, for the block of data, a plurality of costs, each cost corresponding to a different memory unit of the plurality of memory units, wherein each determined cost is based on a tradeoff between reliability of a corresponding memory unit of the plurality of memory units and performance of the corresponding memory unit based on a comparison of the determined failure rates of the memory units to a combination of hotness values that indicate frequency of access of the block of data and latencies of the memory units;

selecting a cost of the plurality of costs, the selected cost being either the highest of the plurality of costs or the lowest of the plurality of costs; and

migrating the block of data to a memory unit of the plurality of memory units that is associated with the selected cost.

16. The non-transitory computer-readable medium of claim 15, wherein the migrating comprises:

responsive to determining that the block of data is not stored in the memory unit that is associated with the selected cost, migrating the block of memory to the memory unit that is associated with the selected cost.