Safety features for high level design

• US 10,366,190 B2
• Filed: 03/29/2018
• Issued: 07/30/2019
• Est. Priority Date: 11/02/2015
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Titley, Adam
• Primary Examiner(s): Levin, Naum
• Application Number:
  US15/940,881
• Publication Number:
  US 20180218094A1
• Time in Patent Office: 488 Days
• CPC Class Codes: G06F 2115/02 System on chip [SoC] design
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level

Abstract

This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with the first safety data type, and generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition. The second representation can be provided in a second language and include at least one safety feature for a portion of the circuit design associated with the at least one construct.

Claims

1. A tangible, non-transitory, and computer-readable medium storing instructions that, when executed by one or more processors, cause one or more processors to:

identify at least one protection version of a data type of an algorithmic description representation of a circuit design, wherein the protection version includes at least one protection mechanism that is based at least in part on the protection version for the data type;

identify at least one programming language construct associated with the protection version of the data type, wherein the algorithmic description representation is specified in a first language; and

generate a second representation of the circuit design based on the algorithmic description representation and a definition for the protection version of the data type, wherein the second representation is specified in a second language and includes at least one protection mechanism that is based at least in part on the protection version of the data type wherein the second representation is used to configure a manufactured programmable logic device after manufacturing of the programmable logic device has been completed.

2. The tangible, non-transitory, and computer-readable medium of claim 1, wherein the algorithmic description representation comprises a control-flow-based representation and wherein the second representation is a data-flow-based representation.

3. The tangible, non-transitory, and computer-readable medium of claim 2, wherein the second language comprises a hardware description language.

4. The tangible, non-transitory, and computer-readable medium of claim 1, wherein the first language comprises a high-level synthesis programming language.

5. The tangible, non-transitory, and computer-readable medium of claim 2, wherein the second representation of the circuit design is a register-transfer level (RTL) representation.

6. The tangible, non-transitory, and computer-readable medium of claim 1, wherein the algorithmic description representation includes one or more directives identifying one or more header files, the one or more header files defining one or more safety data types including the protection version of the data type.

7. The tangible, non-transitory, and computer-readable medium of claim 1, wherein the protection version of the data type specifies a protected function to use the at least one protection mechanism.

8. The tangible, non-transitory, and computer-readable medium of claim 7, wherein the protected function comprises a protection version of a standard function.

9. The tangible, non-transitory, and computer-readable medium of claim 1, wherein the at least one programming construct comprises at least one parameter defined using the protection version of the data type.

10. The tangible, non-transitory, and computer-readable medium of claim 1, wherein the at least one programming language construct comprises at least one pragma directive identifying a function as a protection version a function that is compiled differently than a standard version of the function.

11. The tangible, non-transitory, and computer-readable medium of claim 1, wherein the first language is compatible with a standardized framework for programs that execute across multiple heterogeneous platforms.

12. The tangible, non-transitory, and computer-readable medium of claim 1, wherein the at least one programming language construct incudes at least one function having a return type defined using the protection version of the data type.

13. A system comprising:

one or more memory devices storing instructions;

one or more processing devices configured to execute the instructions to cause the one or more processing devices to;

identify at least one protection version of a data type of an algorithmic description representation of a circuit design, wherein the protection version includes at least one protection mechanism that is based at least in part on the protection version for the data type;

identify at least one programming language construct associated with the protection version of the data type, wherein the algorithmic description representation is specified in a first language; and

generate a second representation of the circuit design based on the algorithmic description representation and a definition for the protection version of the data type, wherein the second representation is specified in a second language and includes at least one protection mechanism that is based at least in part on the protection version of the data type, wherein the second representation is used to configure a manufactured programmable logic device after manufacturing of the programmable logic device has been completed.

14. The system of claim 13, wherein the algorithmic description representation comprises one or more directives identifying one or more header files, the one or more header files define one or more protection versions of data types including the protection version of the data type.

15. The system of claim 14, wherein the instructions cause the one or more processing devices to:

identify the one or more directives;

identify the one or more header files;

access the one or more header files;

retrieve the contents of the one or more header files; and

include the contents of the one or more header files in the algorithmic description representation prior to generating the second representation.

16. The system of claim 13, wherein the at least one programming language construct comprises at least one function including at least one parameter defined using the protection version of the data type.

17. The system of claim 13, wherein the at least one construct includes at least one pragma directive identifying a function as a protected function.

18. A method comprising:

identifying at least one protection version of a data type of an algorithmic description representation of a circuit design, wherein the protection version includes at least one protection mechanism that is based at least in part on the protection version for the data type;

identifying at least one programing language construct associated with the protection version of the data type, wherein the algorithmic description representation is specified in a first language; and

generating a second representation of the circuit design based on the algorithmic description representation and a definition for the protection version of the data type, wherein the second representation is specified in a second language and includes at least one protection mechanism that is based at least in part on the protection version of the data type, wherein the second representation is used to configure a manufactured programmable logic device after manufacturing of the programmable logic device has been completed.

19. The method of claim 18, wherein the algorithmic description representation is a control-flow-based representation and wherein the second representation is a data-flow-based representation.

20. The method of claim 19, wherein the first language comprises a high-level synthesis programming language, and the second representation is a data-flow-based representation.