System for and method of manufacturing a layout design of an integrated circuit

• US 10,366,200 B2
• Filed: 09/07/2016
• Issued: 07/30/2019
• Est. Priority Date: 09/07/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Wei-Cheng, Chen, Chih-Liang, Lai, Chih-Ming, Young, Charles Chew-Yuen, Tzeng, Jiann-Tyng, Sio, Kam-Tou, Liu, Ru-Gun, Peng, Shih-Wei, Chien, Wei-Chen
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): Bowers, Brandon
• Application Number:
  US15/258,932
• Publication Number:
  US 20180068050A1
• Time in Patent Office: 1,056 Days
• Field of Search: 716 52
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes generating a first layout of the integrated circuit based on design criteria, generating a standard cell layout of the integrated circuit, generating a via color layout of the integrated circuit based on the first layout and the standard cell layout and performing a color check on the via color layout based on design rules. The first layout having a first set of vias arranged in first rows and first columns. The standard cell layout having standard cells and a second set of vias arranged in the standard cells. The via color layout having a third set of vias. The third set of vias including a portion of the second set of vias and corresponding locations, and color of corresponding sub-set of vias.

Claims

1. A method of fabricating an integrated circuit, the method comprising:

generating a first layout of the integrated circuit based on design criteria, the first layout having a first set of vias arranged in first rows and first columns, the first rows of the first set of vias being arranged in a first direction, the first columns of the first set of vias being arranged in a second direction different from the first direction, the first set of vias being divided into sub-sets of vias based on a corresponding color, the color indicating that vias of the sub-set of vias with a same color are to be formed on a same mask of a multiple mask set and vias of the sub-set of vias with a different color are to be formed on a different mask of the multiple mask set;

generating a standard cell layout of the integrated circuit, the standard cell layout having standard cells and a second set of vias arranged in the standard cells, each via of the second set of vias being separated from each other by at least a minimum pitch;

generating a via color layout of the integrated circuit based on the first layout and the standard cell layout, the via color layout having a third set of vias, the third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias;

performing a color check on the via color layout based on design rules, and

at least one of the above operations being performed by a hardware processor, and

fabricating the integrated circuit based on at least the via color layout.

2. The method according to claim 1, further comprising:

forming a mask for a corresponding color based on a corresponding via color layout.

3. The method according to claim 1, wherein generating the via color layout based on the first layout and the standard cell layout comprises performing a color mapping between the first layout and the standard cell layout.

4. The method according to claim 3, wherein performing the color mapping between the first layout and the standard cell layout comprises:

adding features of the standard cell layout to a second layout;

adding the colors of features in the first layout to corresponding features in the second layout, and

filtering the second layout based upon the color.

5. The method according to claim 1, wherein the design criteria comprises at least one of:

a mask count;

a via spacing rule;

a layout requirement of the integrated circuit, or

a place and route requirement of the integrated circuit.

6. The method according to claim 5, wherein

the mask count corresponds to a number of masks in the multiple mask set;

the layout requirement includes a minimum spacing between two vias of the second set of vias in a same row or a same column, or

the place and route requirement includes minimum spacing requirements between power plan vias and adjacent vias of the sub-sets of vias, the power plan vias and adjacent vias of the sub-sets of vias are the same color.

7. The method according to claim 6, wherein

the mask count is 3 or more, or

the minimum spacing between the two vias of the second set of vias in the same row or the same column includes:

the two vias of the second set of vias are located in a same column and are separated from each other by at least 2 minimum pitches (P_V) in the second direction;

or

the two vias of the second set of vias are located in a same row and are separated from each other by at least 1 minimum pitch (P_H) in the first direction.

8. The method according to claim 1, wherein the design criteria comprises a first set of spacing requirements including at least one or more of

a minimum via pitch (G0) between each via of the third set of vias in the same mask, G0 being expressed by:

P_poly≤

G0≤

3*P_poly

where P_poly is a minimum pitch between a poly region and an adjacent poly region of the via color layout;

a minimum via pitch (S_HOSH) between a first HOSH via and a first via of the third set of vias, S_HOSH being expressed by;

P_poly≤

S_HOSH≤

3*P_poly

the first HOSH via having an area less than an area of other vias of the third set of vias;

or

a minimum via pitch (G0_HOSH) between the first HOSH via and a second HOSH via of the third set of vias in the same mask, G0_HOSH being expressed by;

0.5*P_poly≤

G0_HOSH≤

2*P_poly

the second HOSH via having an area less than the area of other vias of the third set of vias.

9. The method according to claim 8, wherein the design rules include at least one or more of:

determining if two or more vias of the third set of vias are aligned in the first direction or the second direction;

or

satisfying a second set of spacing requirements for the third set of vias.

10. The method according to claim 9, wherein the second set of spacing requirements comprises at least one or more of:

a via pitch (P_V1) between the first via and a second via of the third set of vias in the same mask, and the first via and the second via are aligned in the second direction, P_V1 being expressed by;

P_V1=P_V*N1

where N1 is a positive integer and pitch P_V is the minimum pitch of at least the via color layout in the second direction;

a via pitch (P_H1) between the first via and a third via of the third set of vias in the same mask, and the first via and the third via are aligned in the first direction,

P_H1=P_H*M*N

where M is a number of masks, N is a positive integer, and pitch P_H is the minimum pitch of at least the via color layout in the first direction;

a pitch (S1) between the second via and the third via, and the second via and the third via are not aligned in the first direction and the second direction, S1 is greater than or equal to S_HOSH;

a pitch (S2) between the first via and the first HOSH via, and the first via and the first HOSH via are not aligned in the first direction and the second direction, S2 is greater than or equal to S_HOSH;

a via pitch (P₁) between the first HOSH via and the second HOSH via, and the first HOSH via and the second HOSH via being aligned in the first direction or the second direction;

P₁ is less than or equal to G0;

P₁ is greater than or equal to G0_HOSH;

or

P_V1 or P_H1 is greater than or equal to G0.

11. A system for manufacturing an integrated circuit, the system comprises:

a non-transitory computer readable medium configured to store executable instructions; and

a processor coupled to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions for;

generating a first layout of the integrated circuit based on at least design criteria, the first layout having a first set of vias arranged in first rows and first columns, the first rows of the first set of vias being arranged in a first direction, the first columns of the first set of vias being arranged in a second direction different from the first direction, the first set of vias being divided into sub-sets of vias based on a corresponding color, the color indicating that vias of the sub-set of vias with a same color are to be formed on a same mask of a multiple mask set and vias of the sub-set of vias with a different color are to be formed on a different mask of the multiple mask set, the design criteria including a mask count corresponding to a number of masks in the multiple mask set;

generating a standard cell layout of the integrated circuit, the standard cell layout having standard cells and a second set of vias arranged in the standard cells, each via of the second set of vias being separated from each other by at least a minimum pitch;

generating a via color layout of the integrated circuit based on the first layout and the standard cell layout, the via color layout having a third set of vias, the third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias;

performing a color check on the via color layout based on design rules; and

,

manufacturing the integrated circuit based on at least the via color layout.

12. The system of claim 11, wherein the processor is configured to execute the instructions for generating the via color layout based on the first layout and the standard cell layout comprises the processor being configured to execute instructions for:

adding the second set of vias and corresponding locations of the standard cell layout to a second layout at same corresponding locations in the second layout;

adding the colors of the first set of vias in the first layout to corresponding vias of the second set of vias in the second layout, and

filtering the second layout based upon the color.

13. The system of claim 11, wherein the processor is configured to execute the instructions for generating the first layout of the integrated circuit based on at least the design criteria, the design criteria further comprising at least one or more of:

a via spacing rule;

a layout requirement of the integrated circuit including a minimum spacing between two vias of the second set of vias in a same row or a same column, or

a place and route requirement of the integrated circuit including minimum spacing requirements between power plan vias and adjacent vias of the sub-sets of vias, the power plan vias and adjacent vias of the sub-sets of vias being the same color.

14. The system of claim 13, wherein the processor is configured to execute the instructions for generating the first layout of the integrated circuit based on at least the design criteria, the design criteria further comprising at least one or more of:

the layout requirement of the integrated circuit including the minimum spacing between the two vias of the second set of vias in the same row or the same column includes;

the two vias of the second set of vias are located in the same column and are separated from each other by at least 2 minimum pitches (P_V) in the second direction;

or

the two vias of the second set of vias are located in the same row and are separated from each other by at least 1 minimum pitch (P_H) in the first direction.

15. The system of claim 11, wherein the processor is configured to execute the instructions for performing the color check on the via color layout based on the design rules, the design rules comprising at least one or more of:

determining if two or more vias of the third set of vias are aligned in the first direction or the second direction;

or

satisfying a set of spacing requirements for the third set of vias.

16. A method of manufacturing an integrated circuit, the method comprising:

generating a first layout of the integrated circuit based on design criteria, the first layout having a first set of vias arranged in first rows and first columns, the first rows of the first set of vias being arranged in a first direction, the first columns of the first set of vias being arranged in a second direction different from the first direction, the first set of vias being divided into sub-sets of vias based on a corresponding color, the color indicating that vias of the sub-set of vias with a same color are to be formed on a same mask of a multiple mask set and vias of the sub-set of vias with a different color are to be formed on a different mask of the multiple mask set;

generating a standard cell layout of the integrated circuit, the standard cell layout having standard cells and a second set of vias arranged in the standard cells, each via of the second set of vias being separated from each other by at least a minimum pitch;

performing a color mapping between the first layout and the standard cell layout thereby generating a via color layout of the integrated circuit, the via color layout having a third set of vias, the third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias;

performing a color check on the via color layout based on design rules comprising determining if two or more vias of the third set of vias are aligned in the first direction or the second direction;

at least one of the above operations being performed by a hardware processor, and

manufacturing the integrated circuit based on at least the via color layout.

17. The method of claim 16, further comprising:

forming a mask for a corresponding color based on a corresponding via color layout.

18. The method of claim 16, wherein the design criteria comprises a first set of spacing requirements including at least one or more of

a minimum via pitch (G0) between each via of the third set of vias in the same mask, G0 being expressed by:

P_poly≤

G0≤

3*P_poly

where P_poly is a minimum pitch between a poly region and an adjacent poly region of the via color layout;

a minimum via pitch (S_HOSH) between a first HOSH via and a first via of the third set of vias, S_HOSH being expressed by;

P_poly≤

S_HOSH≤

3*P_poly

the first HOSH via having an area less than an area of other vias of the third set of vias;

or

a minimum via pitch (G0_HOSH) between the first HOSH via and a second HOSH via of the third set of vias in the same mask, G0_HOSH being expressed by;

0.5*P_poly≤

G0_HOSH≤

2*P_poly

the second HOSH via having an area less than the area of other vias of the third set of vias.

19. The method of claim 16, wherein performing the color mapping between the first layout and the standard cell layout comprises:

adding the standard cells, the second set of vias and corresponding locations of the standard cells and the second set of vias to a second layout at same corresponding locations in the second layout;

for each via in the second set of vias, if a via in the second set of vias has a same location as a via in the first set of vias, adding the color of the via in the first set of vias to a corresponding via in the second layout, and

filtering the second layout based upon the color, wherein each via in the filtered second layout has the same color, the filtered second layout is the via color layout, and the first layout and the standard cell layout have a same size in the first direction and the second direction.

20. The method of claim 16, wherein performing the color check on the via color layout based on the design rules further comprising:

satisfying a set of spacing requirements for the third set of vias.