Devices including first and second buffers, and methods of operating devices including first and second buffers

• US 10,366,646 B2
• Filed: 12/17/2015
• Issued: 07/30/2019
• Est. Priority Date: 12/26/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Kyung-Sang, Lee, Jae-Wook, Kim, Chul-Ho, Lee, Jin-Hyuk
• Primary Examiner(s): Thompson, James A
• Application Number:
  US14/973,296
• Publication Number:
  US 20160189583A1
• Time in Patent Office: 1,321 Days
• Field of Search: None
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Abstract

Devices that include a logic circuit and first and second buffers are provided. The first buffer is spaced apart from the logic circuit by a first distance (and/or is refreshed in a first cycle), and the second buffer is spaced apart from the logic circuit by a second distance that is shorter than the first distance (and/or is refreshed in a second cycle that is different from the first cycle). Moreover, the logic circuit is configured to output, to the first buffer, first data corresponding to fewer toggles than second data that is output from the logic circuit to the second buffer. Methods of operating the devices are also provided.

Claims

1. A semiconductor device comprising:

a logic circuit configured to receive and buffer image data, and to output the image data that is buffered to a display;

first and second frame buffers, the first frame buffer connected to the logic circuit through a first line comprising a first length, and the second frame buffer connected to the logic circuit through a second line comprising a second length longer than the first length; and

conversion circuitry configured to convert the image data into conversion data and to provide the conversion data to the first and second frame buffers,

wherein the image data comprises first image data comprising first and second bit sets different from each other and second image data comprising third and fourth bit sets different from each other,

wherein the conversion circuitry is configured to receive the image data and to convert the image data into first conversion data comprising the first bit set and the third bit set, and into second conversion data comprising the second bit set and the fourth bit set,

wherein the first conversion data is stored in the first frame buffer, and

wherein the second conversion data is stored in the second frame buffer.

2. The semiconductor device of claim 1,

wherein the first frame buffer is at one side of the logic circuit, and

wherein the second frame buffer is at the one side of the logic circuit and is farther than the first frame buffer from the logic circuit.

3. The semiconductor device of claim 1, wherein the conversion circuitry comprises:

a first flip-flop group configured to receive the first bit set of the first image data and the third bit set of the second image data and to output the first bit set of the first image data and the third bit set of the second image data as the first conversion data; and

a second flip-flop group configured to receive the second bit set of the first image data and the fourth bit set of the second image data and to output the second bit set of the first image data and the fourth bit set of the second image data as the second conversion data.

4. The semiconductor device of claim 3, wherein the conversion circuitry is within the logic circuit.

5. The semiconductor device of claim 1, wherein the semiconductor device comprises a display driver integrated circuit (DDI);

and

wherein the image data is supplied from an application processor (AP).

6. The semiconductor device of claim 1,

wherein the first conversion data stored in the first frame buffer is refreshed in a first cycle, and

wherein the second conversion data stored in the second frame buffer is refreshed in a second cycle longer than the first cycle.

7. A semiconductor device comprising:

a logic circuit configured to receive and buffer image data, and to output the image data that is buffered to a display;

first and second frame buffers, the first frame buffer connected to the logic circuit through a first line comprising a first length, and the second frame buffer connected to the logic circuit through a second line comprising a second length longer than the first length; and

conversion circuitry configured to convert the image data into conversion data and to provide the conversion data to the first and second frame buffers,

wherein the image data comprises first image data comprising first and second bit sets different from each other and second image data comprising third and fourth bit sets different from each other,

wherein the conversion circuitry is configured to receive the image data and to convert the image data into first conversion data comprising the first bit set and the third bit set, and into second conversion data comprising the second bit set and the fourth bit set,

wherein the first conversion data is stored in the first frame buffer,

wherein the second conversion data is stored in the second frame buffer,

wherein the first bit set comprises a least significant bit (LSB) set of the first image data,

wherein the second bit set comprises a most significant bit (MSB) set of the first image data,

wherein the third bit set comprises an LSB set of the second image data, and

wherein the fourth bit set comprises an MSB set of the second image data.

8. The semiconductor device of claim 7,

wherein equal numbers of bits are included in the first bit set and the third bit set, and

wherein equal numbers of bits are included in the second bit set and the fourth bit set.

9. A semiconductor device comprising:

an application processor (AP); and

a display driver integrated circuit (DDI) comprising a logic circuit and first and second frame buffers,

wherein the DDI is configured to receive first and second image data from the AP, to convert the first and second image data into first conversion data comprising lower bits of the first and second image data and into second conversion data comprising upper bits of the first and second image data, and to store the first conversion data in the first frame buffer and the second conversion data in the second frame buffer, and

wherein at least one of a distance from the logic circuit to the first and second frame buffers and a refresh cycle for the first and second conversion data stored in the first and second frame buffers is different.

10. The semiconductor device of claim 9,

wherein the DDI further comprises third and fourth frame buffers,

wherein the DDI is further configured to:

receive third and fourth image data from the AP;

convert the third and fourth image data into first conversion data comprising Least Significant Bits (LSBs) of the first to fourth image data, into second conversion data comprising lower bits of the first to fourth image data, into third conversion data comprising upper bits of the first to fourth image data, and into fourth conversion data comprising Most Significant Bits (MSBs) of the first to fourth image data; and

store the first to fourth conversion data in the first to fourth frame buffers, respectively, and

wherein refresh cycles of the third and fourth frame buffers are longer than refresh cycles of the first and second frame buffers.

11. The semiconductor device of claim 10,

wherein the refresh cycle of the fourth frame buffer is longer than the refresh cycle of the third frame buffer, and

wherein the refresh cycle of the second frame buffer is longer than the refresh cycle of the first frame buffer.

12. The semiconductor device of claim 9,

wherein the DDI further comprises third and fourth frame buffers,

wherein the DDI is further configured to:

receive third and fourth image data from the AP;

convert the received third and fourth image data into first conversion data comprising Least Significant Bits (LSBs) of the first to fourth image data, into second conversion data comprising lower bits of the first to fourth image data, into third conversion data comprising upper bits of the first to fourth image data, and into fourth conversion data comprising Most Significant Bits (MSBs) of the first to fourth image data; and

store the first to fourth conversion data in the first to fourth frame buffers, respectively, and

wherein a distance between each of the third and fourth frame buffers and the logic circuit is longer than a distance between each of the first and second frame buffers and the logic circuit.

13. The semiconductor device of claim 12,

wherein the distance between the third frame buffer and the logic circuit is shorter than the distance between the fourth frame buffer and the logic circuit, and

wherein the distance between the first frame buffer and the logic circuit is shorter than the distance between the second frame buffer and the logic circuit.

14. The semiconductor device of claim 9, wherein a refresh cycle of the second frame buffer is longer than a refresh cycle of the first frame buffer.

15. The semiconductor device of claim 9, wherein the second frame buffer is farther than the first frame buffer from the logic circuit.