Memory with a reduced array data bus footprint
First Claim
1. A memory device, comprising:
- a memory array including two or more memory bank groups;
I/O gating circuitry;
a local data bus electrically coupling the I/O gating circuitry to the two or more memory bank groups; and
one or more data latches electrically coupled to the local data bus,wherein—
the local data bus includes a plurality of array data lines shared between the two or more memory bank groups,the plurality of shared array data lines is configured to transfer data between the I/O gating circuitry and each of the two or more memory bank groups,data transferred over the plurality of shared array data lines between the I/O gating circuitry and a first memory bank group in the two or more memory bank groups has a first propagation delay,data transferred over the plurality of shared array data line between the I/O gating circuitry and a second memory bank group in the two or more memory bank groups has a second data propagation delay different than the first propagation delay,the memory device is configured to match column select generations for the first and the second memory bank groups with the first and the second propagation delays, andthe data latches are configured to transfer first data corresponding to a first access operation off of the local data bus to free up the local data bus to transfer second data corresponding to a second access operation.
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Accused Products
Abstract
Memory devices and systems in which array data lines of a local data bus are shared between two or more memory bank groups in a memory array. In one embodiment, a memory device is provided, comprising a memory array, I/O gating circuitry, and a local data bus. The local data bus can include a plurality of array data lines shared between two or more memory bank groups of the memory array. The local data bus can electrically couple and transfer data between the two or more memory bank groups and the I/O gating circuitry. In some embodiments, one or more data latches can be electrically coupled to the local data bus to (i) transfer data off the local data bus to free the plurality of data lines for subsequent data transfers and/or (ii) match varying data propagation timings on the local data with column generations of the memory bank groups.
3 Citations
19 Claims
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1. A memory device, comprising:
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a memory array including two or more memory bank groups; I/O gating circuitry; a local data bus electrically coupling the I/O gating circuitry to the two or more memory bank groups; and one or more data latches electrically coupled to the local data bus, wherein— the local data bus includes a plurality of array data lines shared between the two or more memory bank groups, the plurality of shared array data lines is configured to transfer data between the I/O gating circuitry and each of the two or more memory bank groups, data transferred over the plurality of shared array data lines between the I/O gating circuitry and a first memory bank group in the two or more memory bank groups has a first propagation delay, data transferred over the plurality of shared array data line between the I/O gating circuitry and a second memory bank group in the two or more memory bank groups has a second data propagation delay different than the first propagation delay, the memory device is configured to match column select generations for the first and the second memory bank groups with the first and the second propagation delays, and the data latches are configured to transfer first data corresponding to a first access operation off of the local data bus to free up the local data bus to transfer second data corresponding to a second access operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A memory system, comprising:
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a host device; and a memory device including— a memory array including two or more memory bank groups; I/O gating circuitry; a local data bus electrically coupling the I/O gating circuitry to the two or more memory bank groups; and one or more data latches electrically coupled to the local data bus, wherein— the local data bus includes a plurality of array data lines shared between the two or more memory bank groups, the plurality of shared array data lines is configured to transfer data between the I/O gating circuitry and each of the two or more memory bank groups, data transferred over the plurality of shared array data lines between the I/O gating circuitry and a first memory bank group in the two or more memory bank groups has a first propagation delay, data transferred over the plurality of shared array data line between the I/O gating circuitry and a second memory bank group in the two or more memory bank groups has a second data propagation delay different than the first propagation delay, the memory device is configured to match column select generations for the first and the second memory bank groups with the first and the second propagation delays, and the data latches are configured to transfer first data corresponding to a first access operation off of the local data bus to free up the local data bus to transfer second data corresponding to a second access operation. - View Dependent Claims (14, 15, 16)
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17. An input/output (I/O) circuit for a memory device, the I/O circuit comprising:
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I/O gating circuitry; a local data bus having a plurality of array data lines configured to electrically couple the I/O gating circuitry to two or more memory bank groups in the memory device, the plurality of data lines including— a plurality of array input/output (I/O) data lines; and a plurality of array data mask lines; and one or more data latches electrically coupled to the local data bus, wherein— each of the array data lines in the plurality of array data lines is configured to be shared between the two or more memory bank groups, the plurality of array data lines is configured to transfer data between the I/O gating circuitry and each of the two or more memory bank groups, data transferred over the plurality of array data lines between the I/O gating circuitry and a first memory bank group in the two or more memory bank groups has a first propagation delay, data transferred over the plurality of shared array data lines between the I/O gating circuitry and a second memory bank group in the two or more memory bank groups has a second data propagation delay different than the first propagation delay, and the data latches are configured to isolate first data corresponding to a first data transfer off of the local data bus to free up the local data bus to transfer second data corresponding to a second data transfer. - View Dependent Claims (18, 19)
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Specification