SRAM cell with dynamic split ground and split wordline

• US 10,366,746 B2
• Filed: 01/30/2018
• Issued: 07/30/2019
• Est. Priority Date: 12/02/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wong, Robert C.
• Primary Examiner(s): Le, Thong Q
• Application Number:
  US15/883,389
• Publication Number:
  US 20180158521A1
• Time in Patent Office: 546 Days
• Field of Search: 65154, 36518909, 365156, 365227, 365189011, 36518911, 36523003, 36523006, 36518502, 36518508, 36518511, 36518516, 36518521
• CPC Class Codes: G11C 11/418 Address circuits
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.

Claims

1. A memory cell, comprising:

cross coupled inverters;

a bitline left (BL) which accesses a first inverter of the cross coupled inverters;

a bitline right (BR) which accesses a second inverter of the cross coupled inverters;

a wordline left (WL) which enables a first access transistor;

a wordline right (WR) which enables a second access transistor; and

a split vertical ground line comprising a first vertical ground line (GNDL) separated from a second vertical ground line (GNDR), the GNDL being connected to the first inverter of the cross coupled inverters and the GNDR being connected to the second inverter of the cross coupled inverters,

wherein;

the GNDL and the GNDR are separate vertical SRAM GND buses, and

in a standby mode of the memory cell, Vdd is at an elevated GND (GNDH).

2. The memory cell of claim 1, wherein the GNDH is elevated above GND by 10-15% of the Vdd.

3. The memory cell of claim 1, wherein in the standby mode, the memory cell is idle.

4. The memory cell of claim 1, wherein the GNDR and the GNDL are not strapped together.

5. The memory cell of claim 1, wherein the GNDR and GNDL allow for differential signaling.

6. The memory cell of claim 1, wherein:

the GNDL is connected directly to an NFET of the first inverter; and

the GNDR is connected directly to an NFET of the second inverter.

7. The memory cell of claim 1, further comprising:

a left side cell node (CL) across the first access transistor the BL; and

a right side cell node (CR) across the second access transistor from the BR,

wherein;

during global reset of memory array to zero state, the GNDL is raised to the Vdd to pull down the CR and push up the CL;

during global set of memory array to one state, the GNDR is raised to the Vdd to pull down the CL and push up the CR; and

during global set/reset of specific columns of memory array to specific zero state and one state, the GNDL of specific columns are raised to the Vdd, and the GNDR of other specific columns are raised to the Vdd.

8. The memory cell of claim 1, wherein the cross coupled inverters comprise PFETs and NFETs.

9. The memory cell of claim 8, wherein during read access for the first bitline, the GNDR is raised above GND by about 10% of the Vdd and/or the GNDL is lowered below the GND by about 10% of the Vdd.

10. The memory cell of claim 8, wherein during read access for the second bitline, the GNDL is raised above GND by about 10% of the Vdd and/or the GNDR is lowered below the GND by about 10% of the Vdd.

11. The memory cell of claim 1, wherein:

the BL accesses the first inverter of the cross coupled inverters by enabling the first access transistor, and

the BR accesses the second inverter of the cross coupled inverters by enabling the second access transistor.

12. The memory cell of claim 1, wherein the first access transistor and the second access transistor are NFETs.

13. The memory cell of claim 12, wherein the first inverter and the second inverter further comprise PFETs.

14. The memory cell of claim 1, wherein the GNDR and GNDL are kept common to allow for differential signaling.

15. The memory cell of claim 1, wherein voltage of the GNDR and voltage of the GNDL are independently adjustable around a common GND.