Comparing input data to stored data

• US 10,366,747 B2
• Filed: 11/30/2017
• Issued: 07/30/2019
• Est. Priority Date: 11/30/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Castro, Hernan A.
• Primary Examiner(s): Huang, Min
• Application Number:
  US15/827,019
• Publication Number:
  US 20190164600A1
• Time in Patent Office: 607 Days
• Field of Search: 365148
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 2013/0052 Read process characterized by the shape, e.g. form, length, amplitude of the read pulse
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2213/15 Current-voltage curve
• CPC Class Codes: G11C 2213/73 Array where access device function, e.g. diode function, being merged with memorizing function of memory element
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Abstract

In an example, a method may include comparing input data to stored data stored in a memory cell and determining whether the input data matches the stored data based on whether the memory cell snaps back in response to an applied voltage differential across the memory cell.

Claims

1. A method, comprising:

comparing first input data to first stored data stored in a first memory cell by applying a first voltage differential across the first memory cell during a first time period;

comparing second input data to second stored data stored in a second memory cell by applying a second voltage differential across the second memory cell during a second time period, wherein the first and second voltage differentials have opposite polarities; and

determining whether the first input data matches the first stored data based on whether the first memory cell snaps back in response to applying the first voltage differential across the first memory cell.

2. The method of claim 1, wherein the first memory cell and the second memory cell are part of a group of memory cells and the first and second stored data are part of a stored data vector stored by the group, wherein an input vector comprises the first and second input data, and wherein the method further comprises:

comparing the input vector to the stored data vector;

responsive to determining that any one of the cells in the group snaps back in response to applied voltage differentials across the memory cells in the group, determining a mismatch between the input vector and the stored data vector; and

responsive to determining that none of the cells in the group snaps back in response to the applied voltage differentials, determining a match between the input vector and the stored data vector.

3. The method of claim 1, further comprising determining that the first input data mismatches the first stored data in response to the first memory cell snapping back.

4. The method of claim 3, further comprising, in response to the first memory cell snapping back, storing data in a latch to indicate that the first input data mismatches the first stored data.

5. The method of claim 3, further comprising preventing additional memory cells from snapping back in response to the first memory cell snapping back.

6. The method of claim 3, further comprising preventing comparisons between additional input data and data stored in additional memory cells in response to the first memory cell snapping back.

7. The method of claim 3, further comprising inhibiting current on a signal line coupled to the first memory cell in response to the first memory cell snapping back.

8. The method of claim 1, further comprising determining whether the second input data matches the second stored data based on whether the second memory cell snaps back in response to applying the second voltage differential across the memory cell.

9. The method of claim 1, further comprising:

determining a match between the first input data and the first stored data responsive to the first memory cell not snapping back in response to applying the first voltage differential across the first memory cell.

10. An apparatus, comprising:

a plurality of first signal lines;

a second signal line;

a plurality of memory cells commonly coupled to the second signal line and to respective different ones of the plurality of first signal lines; and

sensing circuitry coupled to the second signal line and configured to indicate that input data mismatches stored data stored in the plurality of memory cells responsive to sensing a snapback event on the second signal line indicative of at least one of the plurality of memory cells snapping back responsive to a first voltage being applied to the plurality of first signal lines and a second voltage being applied to the second signal line;

wherein a difference between the first voltage and the second voltage has a first polarity or a second polarity opposite to the first polarity, and wherein the sensing circuitry comprises a sense amplifier responsive to the first polarity and the second polarity, the sense amplifier configured to sense the snapback event; and

wherein the sensing circuitry further comprises a latch coupled to the sense amplifier and configured to receive a first signal from the sense amplifier responsive to the sense amplifier sensing the snapback event responsive to the first polarity and to receive a second signal from the sense amplifier responsive to the sense amplifier sensing the snapback event responsive to the second polarity, wherein the latch is configured to store a data value, indicating the mismatch between the input data and the stored data, responsive to receiving the first signal or the second signal.

11. The apparatus of claim 10, wherein the sensing circuitry is configured to turn off current to the second signal line responsive to sensing the snapback event on the second signal line.

12. The apparatus of claim 11, wherein turning off the current to the second signal line acts to prevent any other memory cell of the plurality of memory cells from snapping back.

13. The apparatus of claim 10, wherein the latch is configured to:

output a third signal, responsive to receiving the first signal, that causes the apparatus to turn off current to the second signal line; and

output a fourth signal, responsive to receiving the second signal, that causes the apparatus to turn off the current to the second signal line.

14. An apparatus, comprising:

an array comprising snapback memory cells;

a controller coupled to the array and configured to implement an XOR function between an input data value and a data value stored by a memory cell of the array by;

responsive to the input data value being a first value;

applying a first voltage differential across the memory cell, the first voltage differential having a first polarity; and

determining whether the memory cell snaps back in response to the applied first voltage differential; and

responsive to the input data value being a second value;

applying a second voltage differential across the memory cell, the second voltage differential having a second polarity opposite to the first polarity; and

determining whether the memory cell snaps back in response to the applied second voltage differential.

15. The apparatus of claim 14, wherein the controller is configured to:

cause the apparatus to indicate a match between the first value and the stored data value in response to determining that the memory cell does not snap back in response to the applied first voltage differential and to indicate a match between the second value and the stored data value in response to determining that the memory cell does not snap back in response to the applied second voltage differential; and

cause the apparatus to indicate a mismatch between the first value and the stored data value in response to determining that the memory cell snaps back in response to the applied first voltage differential and to indicate a mismatch between the second value and the stored data value in response to determining that the memory cell snaps back in response to the applied second voltage differential.

16. The apparatus of claim 14, wherein the controller is configured to implement ternary functions responsive to the memory cell being in a drifted state, comprising a first threshold voltage having the first polarity and a second threshold voltage having the second polarity, wherein a magnitude of the first threshold voltage is greater than a magnitude of the first voltage differential and a magnitude of the second threshold voltage is greater than a magnitude of the second voltage differential.

17. The apparatus of claim 14, wherein each snapback memory cell is a self-selecting memory cell in which a single material serves as a select element and a storage element.

18. The apparatus of claim 17, wherein single material is a chalcogenide material.

19. The apparatus of claim 14, wherein each snapback memory cell exhibits an asymmetric threshold voltage distribution depending on a polarity of programming.

20. Detection circuitry, comprising:

a first feedback circuit configured to provide feedback to a signal line driver from a latch in association with sensing a snapback memory cell using a first polarity signal;

a second feedback circuit configured to provide feedback to the signal line driver from the latch in association with sensing the snapback memory cell using a second polarity signal; and

wherein the latch is configured to latch a first data value responsive to a snapback event detected by either of the first feedback circuit and the second feedback circuit.

21. The detection circuitry of claim 20, wherein the first and second feedback circuits each comprise a feedback latch.

22. The detection circuitry of claim 20, wherein

the first feedback circuit comprises first circuitry coupled to the signal line driver and configured to receive a first signal from the latch in response to the first feedback circuit detecting a snapback event in response to the memory cell snapping back in response to the first polarity signal being applied across the memory cell;

and

the second feedback circuit comprises second circuitry coupled to the signal line driver and configured to receive a second signal from the latch in response to the second feedback circuit detecting a snapback event in response to the memory cell snapping back in response to the second polarity signal being applied across the memory cell.

23. The detection circuitry of claim 22, wherein the first circuitry is configured to cause the signal line driver to turn off current to the memory cell in response to receiving the first signal from the latch, and the second circuitry is configured to cause the signal line driver to turn off current to the memory cell in response to receiving the second signal from the latch.

24. The detection circuitry of claim 20, wherein

the first feedback circuit comprises pull-down circuitry and the latch comprises first load circuitry coupled to the pull-down circuitry, the first load circuitry coupled to the pull-down circuitry acting as a first comparator;

and

the second feedback circuit comprises pull-up circuitry and the latch comprises second load circuitry coupled to the pull-up circuitry, the second load circuitry coupled to the pull-up circuitry acting as a second comparator.

25. The detection circuitry of claim 20, further comprising switching circuitry coupled to the latch and configured to set operating voltage ranges of the latch.

26. The detection circuitry of claim 20, wherein the first feedback circuit comprises n-channel devices and the second feedback circuit comprises p-channel devices.