Device with dynamic redundancy registers

• US 10,366,774 B2
• Filed: 09/27/2016
• Issued: 07/30/2019
• Est. Priority Date: 09/27/2016
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: El Baraji, Mourad, Berger, Neal, Louie, Benjamin Stanley, Crudele, Lester M., Hillman, Daniel L., Hoberman, Barry
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): Begum, Sultana
• Application Number:
  US15/277,799
• Publication Number:
  US 20180090226A1
• Time in Patent Office: 1,036 Days
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: G11C 29/785 with redundancy programming schemes
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Dynamic redundancy registers for use with a device are disclosed. The dynamic redundancy registers allow a memory bank of the device to be operated with high write error rate (WER). A first level redundancy register (e1 register) is couple to the memory bank. The e1 register may store data words that have failed verification or have not been verified. The e1 register may transfer data words to another dynamic redundancy register (e2 register). The e1 register may transfer data words that have failed to write to a memory bank after a predetermined number of re-write attempts. The e1 register may also transfer data words upon power down.

Claims

1. A method of writing data into a memory device, the method comprising:

writing a data word into a memory bank at a selected one of a plurality of memory addresses, wherein the memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) memory cells, wherein each memory cell is arranged to store a data word at one of a plurality of memory addresses;

verifying the data word written into the memory bank to determine whether the data word was successfully written thereto; and

responsive to a determination that the data word was not successfully written, performing;

writing the data word and the selected one of the plurality of memory addresses into a first level dynamic redundancy register; and

re-writing the data word stored in the first level dynamic redundancy register into the memory bank at the selected one of the plurality of memory addresses.

2. The method of claim 1, further comprising:

performing verification to determine if the data word was successfully written to the memory bank responsive to the re-writing; and

responsive to a determination that the data word was not successfully written during the re-writing, writing the data word and the selected one of the plurality of memory addresses into a second level dynamic redundancy register.

3. The method of claim 2, further comprising:

remapping the data word from the second level dynamic redundancy register to an address in the memory bank, wherein the second level dynamic redundancy register stores a remap address for the data word.

4. The method of claim 2, further comprising:

attempting the re-writing to the memory bank a predetermined number of times prior to writing the data word and the selected one of the plurality of memory addresses into the second level dynamic redundancy register, and wherein the predetermined number is stored using control bits of the first level dynamic redundancy register.

5. The method of claim 4, wherein the attempting the re-writing is performed during a clock cycle in which the memory bank is inactive.

6. The method of claim 1, wherein the memory bank comprises a pseudo-dual port memory bank, wherein the pseudo-dual port memory bank is operable to perform a write operation and a verify operation in a same clock cycle, and wherein the write operation and the verify operation comprise data words that share a common row address.

7. The method of claim 1, wherein the first level dynamic redundancy register comprises a memory selected from a group consisting of:

SRAM, CAM and STT-RAM.

8. The method of claim 1, further comprising:

writing the data word and the selected one of the plurality of memory addresses into a second level dynamic redundancy register on power down, wherein the first level dynamic redundancy register comprises volatile memory, and wherein the second level dynamic redundancy register comprises non-volatile memory.

9. A method of writing data into a memory device, the method comprising:

writing a data word into a memory array at a selected one of a plurality of memory addresses, wherein the memory array comprises a plurality of magnetic random access memory (MRAM) memory cells, wherein each memory cell is arranged to store a data word at one of a plurality of memory addresses;

verifying the data word written into the memory array to determine whether the data word was successfully written thereto; and

responsive to a determination that the data word was not successfully written to memory, performing;

writing the data word and the selected one of the plurality of memory addresses into a first level dynamic redundancy register; and

re-writing the data word stored in the first level dynamic redundancy register into the memory array at the selected one of the plurality of memory addresses.

10. The method of claim 9, further comprising:

performing verification to determine if the data word was successfully written to the memory array responsive to the re-writing; and

responsive to a determination that the data word was not successfully written during the re-writing, writing the data word and the selected one of the plurality of memory addresses into a second level dynamic redundancy register.

11. The method of claim 10, further comprising:

remapping the data word from the second level dynamic redundancy register to an address in the memory array, wherein the second level dynamic redundancy register stores a remap address for the data word.

12. The method of claim 10, further comprising:

attempting the re-writing to the memory array for a predetermined number of times prior to writing the data word and the selected one of the plurality of memory addresses into the second level dynamic redundancy register, and wherein the predetermined number is stored using control bits of the first level dynamic redundancy register.

13. The method of claim 12, wherein the attempting the re-writing is performed during a clock cycle in which the memory array is inactive.

14. The method of claim 9, wherein the memory array comprises a pseudo-dual port memory array, wherein the pseudo-dual port memory array is operable to perform a write operation and a verify operation in a same clock cycle, and wherein the write operation and the verify operation comprise data words that share a common row address.

15. The method of claim 9, wherein the first level dynamic redundancy register comprises a memory selected from a group consisting of:

SRAM, CAM and STT-RAM.

16. The method of claim 9, further comprising:

writing the data word and the selected one of the plurality of memory addresses into a second level dynamic redundancy register on power down, wherein the first level dynamic redundancy register comprises volatile memory, and wherein the second level dynamic redundancy register comprises non-volatile memory.

17. A method of writing data into a memory device, the method comprising:

writing a data word into a memory array at a selected one of a plurality of memory addresses, wherein the memory array comprises a plurality of magnetic random access memory (MRAM) memory cells that are arranged to store a plurality of data words at a plurality of memory addresses, wherein each data word of said plurality of data words is operable to be stored at a respective memory address of said plurality of memory addresses;

verifying the data word written into the memory array to determine whether the data word was successfully written thereto; and

responsive to a determination that the data word was not successfully written to memory, performing;

writing the data word and the selected one of the plurality of memory addresses into a first level dynamic redundancy register; and

re-writing the data word stored in the first level dynamic redundancy register into the memory array at the selected one of the plurality of memory addresses.

18. The method of claim 17, further comprising:

performing verification to determine if the data word was successfully written to the memory array responsive to the re-writing; and

responsive to a determination that the data word was not successfully written during the re-writing, writing the data word and the selected one of the plurality of memory addresses into a second level dynamic redundancy register.

19. The method of claim 18, further comprising:

remapping the data word from the second level dynamic redundancy register to an address in the memory array, wherein the second level dynamic redundancy register stores a remap address for the data word.

20. The method of claim 18, further comprising:

attempting the re-writing to the memory array for a predetermined number of times prior to writing the data word and the selected one of the plurality of memory addresses into the second level dynamic redundancy register, and wherein the predetermined number is stored using control bits of the first level dynamic redundancy register.

21. The method of claim 20, wherein the attempting the re-writing is performed during a clock cycle in which the memory array is inactive.

22. The method of claim 17, wherein the memory array comprises a pseudo-dual port memory array, wherein the pseudo-dual port memory array is operable to perform a write operation and a verify operation in a same clock cycle, and wherein the write operation and the verify operation comprise data words that share a common row address.

23. The method of claim 17, wherein the first level dynamic redundancy register comprises a memory selected from a group consisting of:

SRAM, CAM and STT-RAM.

24. The method of claim 17, further comprising:

writing the data word and the selected one of the plurality of memory addresses into a second level dynamic redundancy register on power down, wherein the first level dynamic redundancy register comprises volatile memory, and wherein the second level dynamic redundancy register comprises non-volatile memory.