Memory device using levels of dynamic redundancy registers for writing a data word that failed a write operation
First Claim
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1. A memory device comprising:
- a memory array of memory cells, wherein the memory array is configured to store a data word at one of a plurality of memory addresses;
a first level dynamic redundancy buffer comprising data storage elements; and
a pipeline coupled to the memory array and the first level dynamic redundancy buffer, wherein the pipeline is configured to;
write a data word into the memory array at a selected one of the plurality of memory addresses;
verify the data word written into the memory array to determine whether the data word was successfully written by the write;
responsive to a determination that the data word was not successfully written by the write, writing the data word and the selected one of the plurality of memory addresses into the first level dynamic redundancy buffer; and
attempt to re-write the data word stored in the first level dynamic redundancy buffer into the memory array at the selected one of the plurality of memory addresses.
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Abstract
Dynamic redundancy buffers for use with a device are disclosed. The dynamic redundancy buffers allow a memory array of the device to be operated with high write error rate (WER). A first level redundancy buffer (e1 buffer) is couple to the memory array. The e1 buffer may store data words that have failed verification or have not been verified. The e1 buffer may transfer data words to another dynamic redundancy buffer (e2 buffer). The e1 buffer may transfer data words that have failed to write to a memory array after a predetermined number of re-write attempts. The e1 buffer may also transfer data words upon power down.
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Citations
24 Claims
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1. A memory device comprising:
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a memory array of memory cells, wherein the memory array is configured to store a data word at one of a plurality of memory addresses; a first level dynamic redundancy buffer comprising data storage elements; and a pipeline coupled to the memory array and the first level dynamic redundancy buffer, wherein the pipeline is configured to; write a data word into the memory array at a selected one of the plurality of memory addresses; verify the data word written into the memory array to determine whether the data word was successfully written by the write; responsive to a determination that the data word was not successfully written by the write, writing the data word and the selected one of the plurality of memory addresses into the first level dynamic redundancy buffer; and attempt to re-write the data word stored in the first level dynamic redundancy buffer into the memory array at the selected one of the plurality of memory addresses. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A memory device comprising:
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a memory array comprising memory cells, wherein the memory array is configured to store a data word at one of a plurality of memory addresses; a first level dynamic redundancy buffer comprising data storage elements; a second level dynamic redundancy buffer comprising data storage elements; and a pipeline coupled to the memory array, the first level dynamic redundancy buffer, and the second level dynamic redundancy buffer, wherein the pipeline is configured to; write a data word into the memory array at a selected one of the plurality of memory addresses; verify the data word written into the memory array to determine whether the data word was successfully written by the write; responsive to a determination that the data word was not successfully written by the write, writing the data word and the selected one of the plurality of memory addresses into the first level dynamic redundancy buffer; re-write the data word stored in the first level dynamic redundancy buffer into the memory array at the selected one of the plurality of memory addresses; perform verification to determine if the data word was successfully written to the memory array responsive to the re-writing; and responsive to a determination that the data was not successfully written during the re-writing, write the data word and the selected one of the plurality of memory addresses into a second level dynamic redundancy buffer. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 24)
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23. A memory device comprising:
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a memory array comprising memory cells, the memory array configured to store a data word at one of a plurality of memory addresses, wherein the memory cells of the memory array comprise a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) cells; a first level dynamic redundancy buffer comprising data storage elements; and a pipeline coupled to the memory array and the first level dynamic redundancy buffer, wherein the pipeline is configured to; write a data word into the memory array at a selected one of the plurality of memory addresses; verify the data word written into the memory array to determine whether the data word was successfully written by the write; responsive to a determination that the data word was not successfully written by the write, writing the data word and the selected one of the plurality of memory addresses into the first level dynamic redundancy buffer; and responsive to a determination that the data was not successfully written, re-write the data word stored in the first level dynamic redundancy buffer into the memory array at the selected one of the plurality of memory addresses.
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Specification