Plated terminations

• US 10,366,835 B2
• Filed: 03/03/2016
• Issued: 07/30/2019
• Est. Priority Date: 04/15/2002
• Status: Active Grant

• Current Assignee: Kyocera AVX Components Corporation (Kyocera Corporation)
• Original Assignee: AVX Corporation (Kyocera Corporation)
• Inventors: Ritter, Andrew P., Heistand, II, Robert H., Galvagni, John L., Dattaguru, Sriram
• Primary Examiner(s): Talbot, Brian K
• Application Number:
  US15/059,984
• Publication Number:
  US 20160189864A1
• Time in Patent Office: 1,244 Days
• Field of Search: None
• CPC Class Codes: C23C 18/1651 Two or more layers only obtained by electroless plating
• CPC Class Codes: C23C 18/1653 Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
• CPC Class Codes: C23C 18/32 Coating with nickel, cobalt or mixtures thereof with phosphorus or boron C23C18/50 takes precedence
• CPC Class Codes: C23C 18/38 Coating with copper
• CPC Class Codes: C23C 18/48 Coating with alloys
• CPC Class Codes: C23C 28/021 including at least one metal alloy layer
• CPC Class Codes: C23C 28/023 only coatings of metal elements only
• CPC Class Codes: C25D 3/56 of alloys
• CPC Class Codes: C25D 5/02 Electroplating of selected surface areas
• CPC Class Codes: C25D 5/34 Pretreatment of metallic surfaces to be electroplated
• CPC Class Codes: C25D 7/00 Electroplating characterised by the article coated
• CPC Class Codes: H01C 1/14 Terminals or tapping points or electrodes specially adapted for resistors in general H01R; Arrangements of terminals or tapping points or electrodes on resistors
• CPC Class Codes: H01C 17/28 adapted for applying terminals
• CPC Class Codes: H01C 7/008 Thermistors H01C7/02 - H01C7/06 take precedence
• CPC Class Codes: H01C 7/10 voltage responsive, i.e. varistors
• CPC Class Codes: H01F 41/04 for manufacturing coils coils for transformer or inductances H01F27/28
• CPC Class Codes: H01G 4/005 Electrodes
• CPC Class Codes: H01G 4/008 Selection of materials
• CPC Class Codes: H01G 4/012 Form of non-self-supporting electrodes
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01G 4/12 : Ceramic dielectrics H01G4/085 takes precedence
• CPC Class Codes: H01G 4/228 : Terminals
• CPC Class Codes: H01G 4/232 : electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/30 : Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H05K 2201/09709 : Staggered pads, lands or terminals; Parallel conductors in different planes
• CPC Class Codes: H05K 3/02 : in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence
• CPC Class Codes: Y10T 29/42 : Piezoelectric device making
• CPC Class Codes: Y10T 29/43 : Electric condenser making
• CPC Class Codes: Y10T 29/435 : Solid dielectric type
• CPC Class Codes: Y10T 29/49002 : Electrical device making
• CPC Class Codes: Y10T 29/49099 : Coating resistive material on a base
• CPC Class Codes: Y10T 29/49101 : Applying terminal

Abstract

Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

Claims

1. A method of electrically connecting a plurality of interior plates of a multilayer ceramic capacitor having a first surface, a second surface opposite the first surface, and additional exterior surfaces, the plurality of interior plates including each of a plurality of electrode layers and a plurality of anchor tabs, edges of at least some of the plurality of the interior plates being exposed upon at least a portion of the first surface of the ceramic capacitor, and where edges of at least some of the plurality of interior plates are also exposed upon at least a portion of the second surface of the capacitor, the method comprising:

electrolessly plating a first layer of electrically-conductive first metal directly onto the first surface including where the edges of the plurality of interior plates are exposed upon the first surface, the first layer of electrically-conductive first metal on the first surface electrically connecting the edges of the plurality of interior plates that are exposed upon the first surface; and

concurrently electrolessly plating a first layer of electrically-conductive first metal directly onto the second surface including where the edges of the plates are exposed upon the second surface, the first layer of electrically-conductive first metal on the second surface electrically connecting the edges of the plurality of interior plates that are exposed upon the second surface,

wherein each of the first layer of electrically-conductive first metal on the first surface and the first layer of electrically-conductive first metal on the second surface is not deposited on any of the additional surfaces which meet the first surface, and

wherein the distance between adjacent exposed edges of adjacent plates in a column is not greater than about ten microns.

2. The method of claim 1, wherein each of electrolessly plating the first layer of electrically-conductive first metal on the first surface and concurrently electrolessly plating the first layer of electrically-conductive first metal on the second surface comprises electrolessly depositing the electrically-conductive first metal by immersing the entire capacitor in a plating solution.

3. The method of claim 2, wherein the electrically-conductive first metal includes at least in part copper (Cu).

4. The method of claim 2, wherein the electrically-conductive first metal includes at least in part nickel (Ni).

5. The method of claim 2, wherein the electrically-conductive first metal includes at least in part copper (Cu) in combination with nickel (Ni).

6. The method of claim 2 further comprising:

plating on top of the electrolessly-deposited electrically-conductive first layer a second-metal layer of an electrically-conductive second metal.

7. The method of claim 6, wherein the plating of the second-metal layer of electrically-conductive second metal comprises:

electroless plating.

8. The method of claim 6, wherein the electrically-conductive second-metal includes at least in part nickel (Ni).

9. The method of claim 6, wherein the plating of the second-metal layer of electrically-conductive second metal comprises:

electrolytic plating.

10. The method of claim 6, further comprising:

plating on top of the electrically-conductive second-metal layer a third-metal layer of electrically-conductive third metal.

11. The method of claim 10, wherein the plating of the third-metal layer of electrically-conductive third metal comprises:

electroless plating.

12. The method of claim 10, wherein the plating of the third-metal layer of electrically-conductive third metal comprises:

electrolytic plating.

13. The method of claim 10, wherein the electrically-conductive third-metal includes at least in part tin (Sn) in combination with lead (Pb).

14. A method of electrically connecting a plurality of interior plates of a multilayer ceramic capacitor having a first surface, a second surface opposite the first surface, and additional exterior surfaces, the plurality of interior plates including each of a plurality of electrode layers and a plurality of anchor tabs, edges of at least some of the interior plates are exposed upon at least a portion of the first surface of the ceramic capacitor, and where edges of at least some of the interior plates are exposed upon at least a portion of the second surface of the capacitor, the method comprising:

electrolessly plating a first layer of electrically-conductive first metal directly onto the first surface including where edges of the plurality of interior plates are exposed upon the first surface by immersing the entire capacitor in a plating solution, the first layer of electrically-conductive first metal on the first surface electrically connecting the edges of the plurality of interior plates that are exposed upon the first surface; and

concurrently electrolessly plating a first layer of electrically-conductive first metal directly onto the second surface including where edges of the plurality of interior plates are exposed upon the second surface while the entire capacitor is immersed in the plating solution, the first layer of electrically-conductive first metal on the second surface electrically connecting the edges of the plurality of interior plates that are exposed upon the second surface,

wherein each of the first layer of electrically-conductive first metal on the first surface and the second layer of electrically-conductive first metal on the second surface extends to a third surface and a fourth surface on top of at least two of the plurality of anchor tabs, and

wherein the distance between adjacent exposed edges of adjacent plates in a column is not greater than about ten microns.

15. The method of claim 14, wherein the electrically-conductive first metal includes at least in part copper (Cu).

16. The method of claim 14, wherein the electrically-conductive first metal includes at least in part nickel (Ni).

17. The method of claim 14, wherein the electrically-conductive first metal includes at least in part copper (Cu) in combination with nickel (Ni).

18. The method of claim 14, further comprising:

plating a second layer of an electrically-conductive second metal on top of the first layer of electrically-conductive first metal that is on the first surface; and

plating a second layer of the electrically-conductive second metal on the first layer of electrically-conductive first metal on the second surface.

19. The method of claim 18, wherein plating the second layer on top of the first layer on the first surface and plating the second layer on top of the first layer on the second surface each comprises electroless plating.

20. The method of claim 18, wherein the electrically-conductive second-metal includes at least in part nickel (Ni).

21. The method of claim 18, wherein the plating of the second-metal layer of electrically-conductive second metal comprises:

electrolytic plating.

22. The method of claim 18, further comprising:

plating on top of the electrically-conductive second-metal layer a third-metal layer of electrically-conductive third metal.

23. The method of claim 22, wherein the plating of the third-metal layer of electrically-conductive third metal comprises:

electroless plating.

24. The method of claim 22, wherein the plating of the third-metal layer of electrically-conductive third metal comprises:

electrolytic plating.

25. The method of claim 22, wherein the electrically-conductive third-metal includes at least in part tin (Sn) in combination with lead (Pb).