Interconnect structure for a microelectronic device

• US 10,366,968 B2
• Filed: 09/30/2016
• Issued: 07/30/2019
• Est. Priority Date: 09/30/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel IP Corporation (Intel Corporation)
• Inventors: Reingruber, Klaus, Wolter, Andreas, Seidemann, Georg, Wagner, Thomas, Waidhas, Bernd
• Primary Examiner(s): Stark, Jarrett J
• Application Number:
  US15/282,855
• Publication Number:
  US 20180096970A1
• Time in Patent Office: 1,033 Days
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/0237 Disposition of the redistribution layers
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06132 being non uniform, i.e. having a non uniform pitch across the array
• CPC Class Codes: H01L 2224/06134 covering only portions of the surface to be connected
• CPC Class Codes: H01L 2224/09177 Combinations of arrays with different layouts
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/17051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 : Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1064 : Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/117 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

Claims

1. A microelectronic device, comprising:

a first semiconductor die having a first group of contacts at a first pitch relative to one another, and a second group of contacts at a second pitch relative to one another, the second pitch being less than the first pitch, wherein at least one of the first and second groups of contacts includes an array of contacts extending along both X and Y dimensions of the first semiconductor die;

a molded component extending over the first semiconductor die;

a redistribution layer having a first side coupled to the first semiconductor die, the redistribution layer having first redistribution layer contacts engaging contacts of the first group of contacts, wherein the redistribution layer includes a dielectric layer formed on both the first semiconductor die and the molded component, and further includes conductive structures supported by the dielectric layer;

a second semiconductor die on the opposite side of the redistribution layer from the first semiconductor die, the second semiconductor device having a third group of contacts at the second pitch, the contacts of the third group of contacts coupled directly to respective contacts of the second group of contacts by direct attachments of respective second and third contacts, of which contacts of at least one of the second and third groups of contacts are in the form of metallic pillars that extend through the redistribution layer to engage the contacts of the other group, and without making electrical connection with the redistribution layer;

and

wherein the second semiconductor die is secured on the opposite side of the redistribution layer from the first semiconductor die, and placed within a vertical dimension established by contact balls on that same opposite side of the redistribution layer from the first semiconductor die, and wherein the contact balls are configured for attaching the microelectronic device to an additional structure.

2. The microelectronic device of claim 1, wherein the second semiconductor device further comprises at least one additional contact outside the third group of contacts.

3. The microelectronic device of claim 2, wherein the additional contact is coupled to a contact of the redistribution layer that is outside a footprint of the first semiconductor die.

4. The microelectronic device of claim 1, wherein the redistribution layer further comprises conductive structures coupling at least some contacts of the first group of contacts to respective contact locations outside a footprint of the first semiconductor die.

5. The microelectronic device of claim 1, wherein the redistribution layer comprises multiple levels of conductive traces.

6. A package for a microelectronic device, comprising:

a first semiconductor die having a first group of contacts at a first pitch relative to one another in both X and Y directions, and a second group of contacts at a second pitch relative to one another in both X and Y directions, the second pitch being less than the first pitch;

a molded structure extending over the first semiconductor die;

a redistribution layer having a first side coupled to the first semiconductor die wherein the redistribution layer includes a dielectric layer formed at least in part on both the molded structure and the first semiconductor die, the redistribution layer further comprising conductive structures supported by the dielectric layer, and the redistribution layer having first redistribution layer contacts engaging contacts of the first group of contacts of the first semiconductor die; and

a second semiconductor die extending on the opposite side of the redistribution layer from the first semiconductor die, the second semiconductor die having a third group of contacts, the contacts of the third group of contacts are arranged at the second pitch in both X and Y directions, and are coupled to respective contacts of the second group of contacts;

wherein contacts of the second group of contacts include metallic pillars extending through the redistribution layer without making electrical connection to conductors within the redistribution layer and coupling to respective contacts of the third group of contacts;

wherein the package further comprises contact balls formed on the redistribution layer and configured to attach the package to another component; and

wherein the second semiconductor die is in an inverted orientation relative to the first semiconductor die, and is located between first and second of the contact balls, and in the vertical space beneath the redistribution layer to which the contact balls extend.

7. The package of claim 6, wherein at least a portion of the contacts of the first group of contacts are connected through the redistribution layer to respective contact balls laterally beyond the lateral dimensions of the first semiconductor die.

8. The package of claim 6, wherein the second semiconductor die comprises at least one additional contact outside the third group of contacts, and wherein the at least one additional contact is coupled to a contact in the redistribution layer.

9. The package of claim 8, wherein one additional contact is coupled to provide only a mechanical connection to the redistribution layer.

10. The package of claim 6, wherein the pitch of the second group of contacts is no more than approximately 70% of the pitch of the first group of contacts.

11. The package of claim 6, wherein the pitch of the second group of contacts is no more than approximately 50% of the pitch of the first group of contacts.

12. An electronic system, comprising:

a microelectronic device, comprising,

a first semiconductor die having a first group of contacts at a first pitch relative to one another, and a second group of contacts at a second pitch relative to one another, the second pitch being less than the first pitch;

a molded component extending over the first semiconductor die;

a redistribution layer formed on both the first semiconductor die and the molded component, the redistribution layer having a first side coupled to the first semiconductor die, the redistribution layer having first redistribution layer contacts engaging contacts of the first group of contacts, wherein the redistribution layer includes a dielectric layer formed on both the first semiconductor die and a molded component, and further includes conductive structures supported by the dielectric; and

a second semiconductor die on the opposite side of the redistribution layer from the first semiconductor die and in partially overlapping relation to the first semiconductor die, the second semiconductor device having a third group of contacts at the second pitch, the contacts of the third group of contacts coupled directly to respective contacts of the second group of contacts, wherein contacts of the second group of contacts include metallic pillars that extend through the redistribution layer to couple to respective contacts of the third group of contacts and without making electrical connection with the redistribution layer;

wherein the redistribution layer includes a dielectric layer formed on both the first semiconductor die and a molded component, and wherein the molded component extends around the first semiconductor die;

and

at least one of a mass storage device and a network interface operably coupled to the microelectronic device.

13. The electronic system of claim 12, wherein the additional contact is outside a footprint of the first semiconductor die.