Semiconductor devices including control logic structures, electronic systems, and related methods
First Claim
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1. A semiconductor device, comprising:
- a stack structure comprising decks, each deck of the stack structure comprising;
a memory element level comprising memory elements;
a control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region and the N-type channel region overlying the first subdeck structure; and
a base control logic structure in electric communication with the stack structure and comprising control logic devices, the control logic level of each individual deck of the stack structure comprising a word line driver in electrical communication with the memory elements of the memory element level of the individual deck of the stack structure.
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Abstract
A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.
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Citations
41 Claims
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1. A semiconductor device, comprising:
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a stack structure comprising decks, each deck of the stack structure comprising; a memory element level comprising memory elements; a control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region and the N-type channel region overlying the first subdeck structure; and a base control logic structure in electric communication with the stack structure and comprising control logic devices, the control logic level of each individual deck of the stack structure comprising a word line driver in electrical communication with the memory elements of the memory element level of the individual deck of the stack structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A semiconductor device, comprising:
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a stack structure comprising multiple decks, each deck of the stack structure comprising; a memory element level comprising memory elements; an access device level comprising access devices electrically connected to the memory elements of the memory element level; and a control logic level comprising; a first subdeck structure comprising a first number of transistors each transistor of the first number of transistors comprising one of an N-type channel region or a P-type channel region, the first subdeck structure comprising a first column decoder; and a second subdeck structure over the first subdeck structure and comprising a second number of transistors, each transistor of the second number of transistors comprising the other of the N-type channel region or the P-type channel region, at least some transistors of the second number of transistors structure electrically coupled to at least some transistors of the first number of transistors, the second subdeck structure comprising a second column decoder. - View Dependent Claims (22, 23, 24, 25, 26, 27)
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28. A semiconductor device, comprising:
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a first deck structure comprising a first memory element level, a first access device level, and a first control logic level comprising a first word line driver; and a second deck structure over the first deck structure, the second deck structure comprising a second memory element level, a second access device level, and a second control logic level comprising a second word line driver, wherein at least one of the first control logic level and the second control logic level comprises at least one CMOS device in electrical communication with a base control logic structure. - View Dependent Claims (29, 30, 31, 32, 33)
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34. A method of forming a semiconductor device, the method comprising:
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forming deck structures over a substrate, wherein forming deck structures comprises forming each deck structure to comprise a memory element level and a control logic level, forming at least one control logic level of at least one deck structure comprising; forming a first subdeck structure comprising first transistors, at least some transistors of the first transistors comprising one of N-type channel regions or P-type channel regions; forming a second subdeck structure comprising second transistors over the first subdeck structure, at least some of the second transistors comprising the other of the N-type channel regions or the P-type channel regions; and electrically connecting the at least some transistors of the first transistors to the at least some transistors of the second transistors to form a device; and forming a base control logic structure comprising control logic devices in electrical communication with the deck structures, wherein forming deck structures comprises forming the control logic level of each individual deck structure to comprise a word line driver in electrical communication with memory elements of the memory element level of the individual deck structure of the deck structures. - View Dependent Claims (35, 36, 37, 38, 39)
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40. An electronic system, comprising:
a memory device in communication with at least one of an electronic signal processor device, an input device, and an output device, the memory device including a stack structure comprising decks, each deck of the stack structure comprising; a memory element level comprising memory elements; and a control logic level in electrical communication with a base control logic structure and the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure over the first subdeck structure and comprising a second number of transistors comprising the other of the P-type channel region and the N-type channel region, the control logic level comprising a word line driver in electrical communication with memory elements of the memory element level.
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41. A method of operating a semiconductor device, the method comprising:
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controlling functions of a stack structure having multiple decks, each deck of the stack structure comprising memory cells using control logic levels of the multiple decks, the control logic levels each comprising at least one multiplexer and at least one control logic device comprising a first subdeck structure comprising transistors having one of a P-type channel region and an N-type channel region overlying a second subdeck structure comprising transistors having the other of the P-type channel region and the N-type channel region; and controlling additional functions of the stack structure using a base control logic structure in electrical communication with the control logic levels of the stack structure.
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Specification