Semiconductor devices including control logic structures, electronic systems, and related methods

• US 10,366,983 B2
• Filed: 12/29/2017
• Issued: 07/30/2019
• Est. Priority Date: 12/29/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Beigel, Kurt D., Sills, Scott E.
• Primary Examiner(s): Hidalgo, Fernando
• Application Number:
  US15/858,128
• Publication Number:
  US 20190206861A1
• Time in Patent Office: 578 Days
• Field of Search: 365 51
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms
• CPC Class Codes: G11C 29/81 using a hierarchical redundancy scheme
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0642 : Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/6675 : Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H03K 19/0948 : using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 19/20 : characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

A semiconductor device includes a stack structure comprising decks. Each deck of the stack structure comprises a memory element level comprising memory elements and control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region or the N-type channel region overlying the first subdeck structure. Related semiconductor devices and methods of forming the semiconductor devices are disclosed.

Claims

1. A semiconductor device, comprising:

a stack structure comprising decks, each deck of the stack structure comprising;

a memory element level comprising memory elements;

a control logic level in electrical communication with the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure comprising a second number of transistors comprising the other of the P-type channel region and the N-type channel region overlying the first subdeck structure; and

a base control logic structure in electric communication with the stack structure and comprising control logic devices, the control logic level of each individual deck of the stack structure comprising a word line driver in electrical communication with the memory elements of the memory element level of the individual deck of the stack structure.

2. The semiconductor device of claim 1, wherein the control logic devices of the base control logic structure exhibit different configurations and have different operational functions than control logic devices of the control logic level of each of the decks of the stack structure.

3. The semiconductor device of claim 1, wherein:

at least one deck of the stack structure comprises control logic devices comprising one or more of local deck decoders, column decoders, row decoders, sense amplifiers, word line drivers, repair devices, memory test devices, multiplexers, error checking and correction devices, and self-refresh devices; and

the control logic devices of the base control logic structure comprise one or more of charge pumps, delay-locked loop devices, and drain supply voltage regulators.

4. The semiconductor device of claim 1, wherein the control logic level of at least one deck of the stack structure is above the memory element level of the at least one deck of the stack structure.

5. The semiconductor device of claim 1, wherein the control logic level of at least one deck of the stack structure is below the memory element level of the at least one deck of the stack structure.

6. The semiconductor device of claim 1, wherein the first number of transistors of at least one deck of the stack structure comprises gate all around transistors.

7. The semiconductor device of claim 1, wherein the first number of transistors of at least one deck of the stack structure comprises single gate transistors.

8. The semiconductor device of claim 1, wherein the first number of transistors of at least one deck of the stack structure comprises gate two side transistors.

9. The semiconductor device of claim 1, wherein the first number of transistors of at least one deck of the stack structure comprises channel regions configured such that current flows in at least one of a lateral direction and a vertical direction.

10. The semiconductor device of claim 1, wherein the first number of transistors of at least one deck of the stack structure comprises at least some transistors that are electrically isolated from other structures in the at least one deck.

11. The semiconductor device of claim 1, wherein the control logic level of each deck in the stack structure is substantially the same.

12. The semiconductor device of claim 1, wherein the first number of transistors and the second number of transistors comprise vertical transistors.

13. The semiconductor device of claim 1, wherein the first number of transistors and the second number of transistors comprise planar transistors.

14. The semiconductor device of claim 1, wherein each deck in the stack structure further comprises an access device level comprising access devices electrically connected to the memory elements of the memory element level.

15. The semiconductor device of claim 1, wherein the control logic level of at least one deck in the stack structure is in electrical communication with the base control logic structure.

16. The semiconductor device of claim 1, wherein the control logic level of at least one deck of the stack structure comprises at least one ring oscillator.

17. The semiconductor device of claim 1, wherein the control logic level of at least one deck of the stack structure comprises at least one inverter.

18. The semiconductor device of claim 1, wherein the control logic level of at least one deck of the stack structure comprises at least one of a balanced inverter, a transmission pass gate, a two-input NAND circuit, and a balanced two-input NAND circuit.

19. The semiconductor device of claim 1, wherein the first subdeck structure of at least one of the decks of the stack structure comprises vertical NMOS transistors and the second subdeck structure of the at least one deck of the stack structure comprises vertical PMOS transistors.

20. The semiconductor device of claim 1, wherein the transistors comprising a P-type channel region comprise an N-type source region, an N-type drain region, and the P-type channel region between the N-type source region and the N-type drain region, the P-type channel region extending in a direction substantially parallel with a major surface of a substrate of the semiconductor device.

21. A semiconductor device, comprising:

a stack structure comprising multiple decks, each deck of the stack structure comprising;

a memory element level comprising memory elements;

an access device level comprising access devices electrically connected to the memory elements of the memory element level; and

a control logic level comprising;

a first subdeck structure comprising a first number of transistors each transistor of the first number of transistors comprising one of an N-type channel region or a P-type channel region, the first subdeck structure comprising a first column decoder; and

a second subdeck structure over the first subdeck structure and comprising a second number of transistors, each transistor of the second number of transistors comprising the other of the N-type channel region or the P-type channel region, at least some transistors of the second number of transistors structure electrically coupled to at least some transistors of the first number of transistors, the second subdeck structure comprising a second column decoder.

22. The semiconductor device of claim 21, wherein the control logic level of at least one of the decks of the multiple decks of the stack structure comprises at least one inverter.

23. The semiconductor device of claim 21, wherein a gate electrode of at least one transistor of the first number of transistors is in electrical communication with a gate electrode of a respective transistor of the second number of transistors through a gate contact extending between the first subdeck structure and the second subdeck structure.

24. The semiconductor device of claim 21, wherein the first number of transistors comprises vertical transistors and the second number of transistors comprises vertical transistors.

25. The semiconductor device of claim 21, wherein the control logic level of at least one deck of the multiple decks comprises at least one of an inverter, a two-input NAND circuit, a balanced inverter, a balanced two-input NAND circuit, and a ring oscillator.

26. The semiconductor device of claim 25, wherein an output structure of the at least one of a inverter, a two-input NAND circuit, a balanced inverter, a balanced two-input NAND circuit, and a ring oscillator is located vertically between the first subdeck structure and the second subdeck structure.

27. The semiconductor device of claim 21, wherein the channel region of at least one transistor of the first number of transistors extends in a lateral direction.

28. A semiconductor device, comprising:

a first deck structure comprising a first memory element level, a first access device level, and a first control logic level comprising a first word line driver; and

a second deck structure over the first deck structure, the second deck structure comprising a second memory element level, a second access device level, and a second control logic level comprising a second word line driver,

wherein at least one of the first control logic level and the second control logic level comprises at least one CMOS device in electrical communication with a base control logic structure.

29. The semiconductor device of claim 28, wherein the first control logic level is substantially the same as the second control logic level.

30. The semiconductor device of claim 28, wherein at least one of the first control logic level and the second control logic level comprises transistors having one of N-type channel regions or P-type channel regions over transistors having the other of the N-type channel regions or the P-type channel regions.

31. The semiconductor device of claim 30, wherein the N-type channel regions and the P-type channel regions extend in a vertical direction relative to the base control logic structure.

32. The semiconductor device of claim 30, wherein the N-type channel regions and the P-type channel regions extend in a lateral direction relative to the base control logic structure.

33. The semiconductor device of claim 28, further comprising a third deck structure over the second deck structure, the third deck structure comprising a third memory element level, a third access device level, and a third control logic level.

34. A method of forming a semiconductor device, the method comprising:

forming deck structures over a substrate, wherein forming deck structures comprises forming each deck structure to comprise a memory element level and a control logic level, forming at least one control logic level of at least one deck structure comprising;

forming a first subdeck structure comprising first transistors, at least some transistors of the first transistors comprising one of N-type channel regions or P-type channel regions;

forming a second subdeck structure comprising second transistors over the first subdeck structure, at least some of the second transistors comprising the other of the N-type channel regions or the P-type channel regions; and

electrically connecting the at least some transistors of the first transistors to the at least some transistors of the second transistors to form a device; and

forming a base control logic structure comprising control logic devices in electrical communication with the deck structures, wherein forming deck structures comprises forming the control logic level of each individual deck structure to comprise a word line driver in electrical communication with memory elements of the memory element level of the individual deck structure of the deck structures.

35. The method of claim 34, wherein forming a first subdeck structure comprises forming an N-type source material, forming a P-type channel material over the N-type source material, forming an N-type drain material over the P-type channel material and patterning the N-type source material, the P-type channel material, and the N-type drain material to form the first transistors to comprise vertical transistors.

36. The method of claim 34, wherein forming a first subdeck structure comprises forming a sacrificial material over the first transistors.

37. The method of claim 36, further comprising removing the sacrificial material from over surfaces of the first transistors and forming conductive contacts over the first transistors.

38. The method of claim 34, wherein forming a first subdeck structure comprises forming the first transistors to comprise planar transistors.

39. The method of claim 34, wherein electrically connecting the at least some transistors of the first transistors to the at least some transistors of the second transistors to form a device comprises forming at least one of an inverter, a two-input NAND circuit, a balanced inverter, a balanced two-input NAND circuit, and a ring oscillator.

40. An electronic system, comprising:

a memory device in communication with at least one of an electronic signal processor device, an input device, and an output device, the memory device including a stack structure comprising decks, each deck of the stack structure comprising;

a memory element level comprising memory elements; and

a control logic level in electrical communication with a base control logic structure and the memory element level, the control logic level comprising a first subdeck structure comprising a first number of transistors comprising a P-type channel region or an N-type channel region and a second subdeck structure over the first subdeck structure and comprising a second number of transistors comprising the other of the P-type channel region and the N-type channel region, the control logic level comprising a word line driver in electrical communication with memory elements of the memory element level.

41. A method of operating a semiconductor device, the method comprising:

controlling functions of a stack structure having multiple decks, each deck of the stack structure comprising memory cells using control logic levels of the multiple decks, the control logic levels each comprising at least one multiplexer and at least one control logic device comprising a first subdeck structure comprising transistors having one of a P-type channel region and an N-type channel region overlying a second subdeck structure comprising transistors having the other of the P-type channel region and the N-type channel region; and

controlling additional functions of the stack structure using a base control logic structure in electrical communication with the control logic levels of the stack structure.