Replacement metal gate and inner spacer formation in three dimensional structures using sacrificial silicon germanium

• US 10,367,061 B1
• Filed: 03/30/2018
• Issued: 07/30/2019
• Est. Priority Date: 03/30/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Loubet, Nicolas
• Primary Examiner(s): Ho, Tu-Tu V
• Application Number:
  US15/941,525
• Time in Patent Office: 487 Days
• Field of Search: 257347
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A technique relates to a semiconductor device. Stacks are formed each of which including two or more nanosheets separated by a high-k dielectric material. The high-k dielectric material is formed on at least a center portion of the two or more nanosheets in the stacks. A lower spacer material is on a periphery of the two or more nanosheets, and an upper spacer material is on the lower spacer material such that the upper spacer material is above a top one of the two or more nano sheets. Source and drain regions are formed on sides of the stacks.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming stacks each of which including two or more nanosheets separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanosheets in the stacks, wherein a lower spacer material is on a periphery of the two or more nanosheets, wherein the lower spacer material is on a top surface of an upper most nanosheet of the two or more nanosheets, wherein an upper spacer material is directly on the lower spacer material such that the upper spacer material is above a top one of the two or more nanosheets; and

forming source and drain regions on sides of the stacks.

2. The method of claim 1, wherein the lower spacer material and the upper spacer material are different materials.

3. The method of claim 1, wherein the lower spacer material and the upper spacer material are the same materials.

4. The method of claim 1, wherein the lower spacer material is formed by removing a sacrificial material having been formed after formation of the upper spacer material and depositing the lower spacer material in a space left from removal of the sacrificial material.

5. The method of claim 1, wherein the lower spacer material is formed after dummy gate formation and after formation of the upper spacer material.

6. The method of claim 1, wherein the stacks are formed on fin-like structures, the fin-like structures being formed to have a fin pitch, the fin-like structures having been formed in a substrate.

7. The method of claim 6, wherein the fin pitch is about 5 to 50 nanometers.

8. The method of claim 6, wherein the upper spacer material is formed on a portion of a sacrificial material, the sacrificial material being formed to accommodate the fin pitch.

9. The method of claim 8, wherein removal of the portion of the sacrificial material provides a location to form the lower spacer material underneath the upper spacer material.

10. A method of forming a semiconductor device, the method comprising:

forming two or more nanosheets in a stack, the two or more nanosheets being separated by a high-k dielectric material in the stack;

forming an upper spacer material above a top one of the two or more nanosheets in the stack;

forming a lower spacer material at least on a periphery of the two or more nanosheets such that the lower spacer material is below the upper spacer material in the stack, wherein the lower spacer material is on a top surface of an upper most nanosheet of the two or more nanosheets, wherein the upper spacer material is directly on the lower spacer material; and

forming source and drain regions on sides of the stack.

11. The method of claim 10, wherein the lower spacer material and the upper spacer material are different materials.

12. The method of claim 10, wherein the lower spacer material and the upper spacer material are the same materials.

13. The method of claim 10, wherein the lower spacer material is formed by removing a sacrificial material having been formed after formation of the upper spacer material and depositing the lower spacer material in a space left from removal of the sacrificial material.

14. The method of claim 10, wherein the lower spacer material is formed after dummy gate formation and after formation of the upper spacer material.

15. The method of claim 10, wherein the stack is formed on fin-like structures, the fin-like structures being formed to have a fin pitch.

16. The method of claim 15, wherein:

the upper spacer material is formed on a portion of a sacrificial material, the sacrificial material being formed to accommodate the fin pitch; and

removal of the portion of the sacrificial material provides a location to form the lower spacer material underneath the upper spacer material.

17. The method of claim 16, wherein the fin pitch is about 5 to 50 nanometers.

18. A semiconductor device comprising:

stacks each of which including two or more nanosheets separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanosheets in the stacks, wherein a lower spacer material is on a periphery of the two or more nanosheets, wherein the lower spacer material is on a top surface of an upper most nanosheet of the two or more nanosheets, wherein an upper spacer material is directly on the lower spacer material such that the upper spacer material is above a top one of the two or more nanosheets; and

source and drain regions on sides of the stacks.

19. The semiconductor of claim 18, wherein the lower spacer material and the upper spacer material are different materials.

20. The semiconductor of claim 18, wherein the lower spacer material and the upper spacer material are the same materials.