Suppression of noise up-conversion mechanisms in LC oscillators

• US 10,367,513 B2
• Filed: 11/30/2017
• Issued: 07/30/2019
• Est. Priority Date: 11/30/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ferriss, Mark A., Friedman, Daniel J., Sadhu, Bodhisatwa, Lee, Wooram
• Primary Examiner(s): Jager, Ryan
• Application Number:
  US15/826,875
• Publication Number:
  US 20190165796A1
• Time in Patent Office: 607 Days
• Field of Search: 327159
• CPC Class Codes: H03B 2200/0062 Bias and operating point
• CPC Class Codes: H03B 2200/009 Reduction of phase noise
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1243 the means comprising voltage variable capacitance diodes
• CPC Class Codes: H03B 5/129 the parameter being a bias voltage or a power supply
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence

Abstract

A phase-locked loop circuit includes an oscillator, a frequency control device, the frequency control device generating a frequency control signal that controls a frequency of the oscillator, and a bias optimizer that monitors the frequency control device and generates a bias voltage for the oscillator, the oscillator includes a transfer function from bias voltage to frequency that is proportional to a transfer function from a low frequency noise component to frequency, the transfer function from bias voltage to frequency having a convex shape with a local minimum at which a sensitivity of the frequency to changes in the bias voltage is zero, and the bias voltage from the bias optimizer is set to the local minimum.

Claims

1. A phase-locked loop (PLL) circuit comprising:

an oscillator;

a frequency control device, the frequency control device generating a frequency control signal that controls a frequency of the oscillator; and

a bias optimizer that monitors the frequency control device and generates a bias voltage for the oscillator,

wherein the oscillator includes a transfer function from bias voltage to frequency that is proportional to a transfer function from a low frequency noise component to frequency, the transfer function from bias voltage to frequency having a convex shape with a local minimum at which a sensitivity of the frequency to changes in the bias voltage is zero, and wherein the bias voltage from the bias optimizer is set to the local minimum.

2. The PLL circuit of claim 1, wherein the oscillator comprises:

an analog varactor structure for controlling the frequency of the oscillator;

a plurality of controllable caps;

a choke inductor, the choke inductor provides a DC current to a transistor independent of a gate bias;

a power supply Vdd connected to a center tap of the choke inductor;

a tank inductor, wherein a center tap of the tank inductor is controlled by the bias optimizer; and

a coupling cap for providing that a DC value of a voltage in the transistor is decoupled from the bias voltage.

3. The PLL circuit of claim 1, further comprising:

an analog proportional path controlling a capacitance of an analog varactor structure in the oscillator; and

an integral path controlling a plurality of controllable caps in the oscillator.

4. The PLL circuit of claim 1, wherein the oscillator comprises a voltage controlled oscillator.

5. The PLL circuit of claim 1, wherein at a frequency close to DC, a common mode component of transistor noise is in series with the bias voltage.

6. The PLL circuit of claim 1, wherein up-conversion of a differential component of transistor noise is suppressed by a symmetry of the oscillator.

7. A method for suppressing noise up-conversion, the method comprising:

providing a phase-locked loop (PLL) circuit comprising;

an oscillator;

a frequency control device, the frequency control device generating a frequency control signal that controls a frequency of the oscillator; and

a bias optimizer that monitors the frequency control device and generates a bias voltage for the oscillator,

wherein the oscillator includes a transfer function from bias voltage to frequency that is proportional to a transfer function from a low frequency noise component to frequency, the transfer function from bias voltage to frequency having a convex shape with a local minimum at which a sensitivity of the frequency to changes in the bias voltage is zero;

determining the local minimum of the transfer function from bias voltage to frequency; and

setting the bias voltage from the bias optimizer to the local minimum.

8. The method of claim 7, wherein determining the local minimum of the transfer function from bias voltage to frequency comprises:

setting the bias voltage to a maximum value;

allowing the PLL circuit to reach a steady-state frequency;

recording, by the bias optimizer, a first frequency control signal;

reducing, by the bias optimizer, the bias voltage by a differential amount, wherein a change to the bias voltage results in a change to the frequency of the oscillator;

allowing the PLL circuit to reach a steady-state frequency;

recording, by the bias optimizer, a second frequency control signal;

calculating, by the bias optimizer, a difference between the first frequency control signal and the second frequency control signal,

wherein the difference between the first frequency control signal and the second frequency control signal divided by the differential amount comprises a measure of a bias voltage to frequency transfer function gradient; and

reducing the bias voltage by an amount proportional to the bias voltage to frequency transfer function gradient until the difference between the first frequency control signal and the second frequency control signal is equal to zero.

9. The method of claim 7, wherein the first frequency control signal and the second frequency control signal are recorded on an integral path of the PLL circuit.

10. The method of claim 9, wherein a gain of the integral path of the oscillator is constant.

11. The method of claim 7, wherein the difference between the first frequency control signal and the second frequency control signal corresponds to an amount the PLL circuit changed the first frequency control signal to correct for changes in the bias voltage.

12. The method of claim 7, wherein the difference between the first frequency control signal and the second frequency control signal is equal to zero when a minimum sensitivity point has been reached, the minimum sensitivity point comprises a point at which changes to the bias voltage do not affect the frequency of the oscillator, wherein the first frequency control signal and the second frequency control signal are equal at the minimum sensitivity point.

13. The method of claim 7, wherein the bias voltage asymptotically approaches the local minimum.

14. The method of claim 7, wherein the frequency of the oscillator comprises a non-stationary frequency, and determining the local minimum further comprises:

initializing an average bias voltage to a maximum voltage value and an average sensitivity of the bias voltage to zero;

applying a first bias step according to a frequency waveform;

recording frequency control signals at times corresponding to minimum frequency points and maximum frequency points; and

updating the average bias voltage and the average sensitivity of the bias voltage with a step proportional to a difference between the recorded frequency control signals at minimum frequency and maximum frequency points.

15. The method of claim 14, wherein the non-stationary frequency of the oscillator comprises a Frequency Modulated Continuous Wave (FMCW).

16. The method of claim 7, wherein the oscillator comprises:

an analog varactor structure controlling the frequency of the oscillator;

a plurality of controllable caps;

a choke inductor, the choke inductor provides a DC current to a transistor independent of a gate bias;

a power supply Vdd connected to a center tap of the choke inductor;

a tank inductor, wherein a center tap of the tank inductor is controlled by the bias optimizer; and

a coupling cap for providing that a DC value of a voltage in the transistor is decoupled from the bias voltage.

17. The method of claim 7, wherein the PLL circuit further comprises:

an analog proportional path controlling a capacitance of an analog varactor structure in the oscillator; and

an integral path controlling a plurality of controllable caps in the oscillator.

18. The method of claim 7, wherein the oscillator comprises a voltage controlled oscillator.

19. The method of claim 7, wherein at a frequency close to DC, a common mode component of transistor noise is in series with the bias voltage.

20. The method of claim 7, wherein up-conversion of a differential component of transistor noise is suppressed by a symmetry of the oscillator.