Passive phased injection locked circuit

• US 10,367,514 B2
• Filed: 05/22/2015
• Issued: 07/30/2019
• Est. Priority Date: 01/24/2015
• Status: Active Grant

• Current Assignee: Circuit Seed, LLC
• Original Assignee: Circuit Seed, LLC
• Inventors: Schober, Susan Marya, Schober, Robert C., Shapiro, Herbert
• Primary Examiner(s): Tran, Khanh C
• Application Number:
  US15/545,893
• Publication Number:
  US 20180019757A1
• Time in Patent Office: 1,530 Days
• CPC Class Codes: H03B 5/12 active element in amplifier being semiconductor device H03B5/14 takes precedence
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/0322 with differential cells
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 2207/10 Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path
• CPC Class Codes: H03L 7/04 wherein the frequency-determining element comprises distributed inductance and capacitance
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

The present invention relates to passive phased injection locked circuit and ring-based voltage controlled oscillators. A passive phased injection locked circuit comprises first and second transmission lines, each has a plurality of discrete elements, that are operative to delay the phase of AC signal. Between the first and second transmission lines, a capacitor network is formed to advance the phases of the AC signal in concert along the transmission lines. For the ring-based voltage controlled oscillators, each of the first and second transmission lines has an odd number of discrete elements.

Claims

1. A passive phased injection locked circuit comprising:

first and second transmission lines, said first transmission line comprises a plurality of current-starved inverters, and said second transmission line comprises a corresponding number of current-starved inverters to said first transmission line;

each of said first and second transmission lines comprising

1) an input and an output; and

2) said current-starved inverters connected electrically in series between said input and said output, each of said current-starved inverters being operative to delay said phase of AC signal applied to said input;

wherein an output of one of said current-starved inverters in said first or second transmission line is capacitively coupled to said input of said next higher corresponding one of said current-starved inverters in said other transmission line to form a network between said first and second transmission lines, said network being operative to advance said phases of said applied AC signal in concert along said transmission line.

2. A circuit as in claim 1 wherein said each of said first and second transmission lines comprise an odd number of said current-starved inverters.

3. A circuit as in claim 1 wherein said each of said current-starved inverter stages comprises:

a. a first PMOS transistor,

b. a second PMOS transistor,

c. a first NMOS transistor, and

d. a second NMOS transistor,

wherein said first and second PMOS transistors and said first and second NMOS transistors are arranged to be symmetrically self-biased around midpoint.

4. A circuit as in claim 3 wherein said each of said first and second PMOS transistors and said first and second NMOS transistors comprises:

a gate, a source, and a drain;

wherein said drain of said first PMOS is in communication with said source of said second PMOS;

said drain of said first PMOS is in communication with said source of said second PMOS;

said drain of said second PMOS is in communication with said drain of said first NMOS to form said output of said each of said current-starved inverters; and

said source of said first NMOS is in communication with said drain of said second NMOS; and

said gate of said second PMOS and said gate of said first NMOS are connected together to receive said output of said next lower corresponding one of said current-starved inverters in said other transmission line.

5. A circuit as in claim 4 wherein said gate of said first PMOS or said gate of said second NMOS as said input of said each of said current-starved inverters to control frequency and phase of said output of said each of said current-starved inverters.

6. A circuit as in claim 1 further comprises a plurality of capacitors, each of said plurality of capacitors connects said output of one of said elements current-starved inverters in said first or second transmission line with said input of said next higher corresponding one of said elements current-starved inverters in said other transmission line.

7. A voltage controlled oscillator comprising first and second ring oscillators, said first ring oscillators comprising one or more odd number of current-starved inverter stages, and second ring oscillators comprising a corresponding number of current-starved inverter stages to said first oscillators, said current-starved inverter stages of each of said first and second ring oscillators being connected electrically in series between an input and an output of said each of said first and second ring oscillators, said output of each of said first and second ring oscillators being electrically connected to said input thereof, said input of each of said current-starved inverter stages of one of said first or second ring oscillators having a connection to said output of said corresponding one of said current-starved inverter stages of said other one of first and second ring oscillators, said connection comprising a capacitor for forming a capacitor network between said first and second ring oscillators operative to tune said first and second ring oscillators responsive to a first signal applied to said input of said first ring oscillators or second signal applied to said input of said second ring oscillators.

8. A voltage controlled oscillator as in claim 7 wherein said each of said current-starved inverter stages comprises:

a. a first PMOS transistor,

b. a second PMOS transistor,

c. a first NMOS transistor, and

d. a second NMOS transistor,

wherein said first and second PMOS transistors and said first and second NMOS transistors are arranged to be symmetrically self-biased around midpoint.

9. A voltage controlled oscillator as in claim 8 wherein said each of said first and second PMOS transistors and said first and second NMOS transistors comprises:

a gate, a source and a drain;

wherein said drain of said first PMOS is in communication with said source of said second PMOS;

said drain of said first PMOS is in communication with said source of said second PMOS;

said drain of said second PMOS is in communication with said drain of said first NMOS to form said output of said each of said current-starved inverter stages; and

said source of said first NMOS is in communication with said drain of said second NMOS; and

said gate of said second PMOS and said gate of said first NMOS are connected together to receive said output of said next lower corresponding one of said current-starved inverters in another one of said first ring oscillator or said second ring oscillator.

10. A voltage controlled oscillator as in claim 9 wherein said gate of said first PMOS or said gate of said second NMOS as said input of said each of said current-starved inverters to control frequency and phase of said output of said each of said current-starved inverters.

11. A tuned multiple-row voltage controlled oscillator, comprising:

a plurality of ring oscillators, each of said plurality of said ring oscillators comprising one or more odd number of current-starved inverter stages and all of said plurality of said ring oscillators have said same number of said current-starved inverter stages,

said current-starved inverter stages of each of said plurality of said ring oscillators being connected electrically in series between an input and an output of said each of said plurality of said ring oscillators,

said output of each of said plurality of said ring oscillators being electrically connected to said input thereof,

said input of each of said current-starved inverter stages of one of said plurality of said ring oscillators having a connection to said output of said corresponding adjacent one of said current-starved inverter stages of said other one of said plurality of said ring oscillators,

said connection comprising a capacitor for forming a capacitor network between said one and said adjacent one of said plurality of said ring oscillators operative to tune said plurality of said ring oscillators responsive to a plurality of signals applied to said inputs of said plurality of said ring oscillators.

12. A tuned multiple-row voltage controlled oscillator as in claim 11, wherein said each of said current-starved inverter stages comprises:

a. a first PMOS transistor,

b. a second PMOS transistor,

c. a first NMOS transistor, and

d. a second NMOS transistor

wherein said first and second PMOS transistors and said first and second NMOS transistors are arranged to be symmetrically self-biased around midpoint.

13. A tuned multiple-row voltage controlled oscillator as in claim 12, wherein said each of said first and second PMOS transistors and said first and second NMOS transistors comprises:

a gate, a source and a drain;

wherein said drain of said first PMOS is in communication with said source of said second PMOS;

said drain of said first PMOS is in communication with said source of said second PMOS;

said drain of said second PMOS is in communication with said drain of said first NMOS to form said output of said each of said current-starved inverter stages; and

said source of said first NMOS is in communication with said drain of said second NMOS; and

said gate of said second PMOS and said gate of said first NMOS are connected together to receive said output of said next lower corresponding one of said current-starved inverters in another one of said one or said adjacent one of said plurality of said ring oscillators.

14. A tuned multiple-row voltage controlled oscillator as in claim 13, wherein said gate of said first PMOS or said gate of said second NMOS as said input of said each of said current-starved inverters to control frequency and phase of said output of said each of said current-starved inverters.