Techniques for non-blocking control information and data synchronization by a data storage device

• US 10,372,351 B2
• Filed: 02/23/2017
• Issued: 08/06/2019
• Est. Priority Date: 02/23/2017
• Status: Active Grant

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Frid, Marina, Genshaft, Igor
• Primary Examiner(s): Gebril, Mohamed M
• Application Number:
  US15/440,394
• Publication Number:
  US 20180239545A1
• Time in Patent Office: 894 Days
• Field of Search: 711103
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 2212/1008 Correctness of operation, e.g. memory ordering
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/65 Details of virtual memory and virtual address translation
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send control information to a host device. The control information is associated with first parity information. The controller further includes a circuit configured to determine second parity information associated with the control information. The controller is configured to terminate and optionally rollback an operation associated with the control information in response to the first parity information differing from the second parity information. The terminated optionally rolled-back operation associated with the control information may be a non-blocking control sync operation.

Claims

1. An apparatus comprising:

a non-volatile memory; and

a controller coupled to the non-volatile memory, the controller including;

an interface configured to send control information to a host device, the control information associated with first parity information; and

a circuit configured to determine second parity information associated with the control information,

wherein the controller is configured to terminate an operation associated with the control information in response to the first parity information differing from the second parity information, and

wherein the controller further includes a dual layer flash translation layer (FTL) having a first control information layer and a second control information layer, and wherein a first operation to store the control information to the non-volatile memory and a second operation to store mapping information to the controller during the first operation are non-blocking operations enabled by the first control information layer and the second control information layer.

2. The apparatus of claim 1, further comprising a comparator configured to compare the first parity information and the second parity information.

3. The apparatus of claim 1, wherein the first parity information and the second parity information include exclusive-or (XOR) values.

4. The apparatus of claim 1, further comprising a volatile memory configured to store the first parity information, wherein the interface is further configured to send the control information to a memory of the host device.

5. The apparatus of claim 4, wherein the controller is further configured to operate the memory of the host device as a virtual extension of the volatile memory.

6. The apparatus of claim 1, wherein the first control information layer and the second control information layer are split into regions, and wherein the first operation to store the control information to the non-volatile memory is associated with regions from both the first control information layer and the second control information layer.

7. The apparatus of claim 6, wherein the controller is further configured to selectively update the first control information layer or the second control information layer in regions that are not included in the first operation to store the control information to the non-volatile memory.

8. The apparatus of claim 1, wherein the terminated operation associated with the control information corresponds to the first operation to store the control information to the non-volatile memory in a non-blocking manner.

9. The apparatus of claim 1, wherein the controller is further configured to perform a rollback operation in response to termination of the first operation to store the control information to the non-volatile memory.

10. A method of operation of a data storage device, the method comprising:

sending data from a controller of a data storage device to a memory of a host device;

determining first parity information associated with the data before the data is sent to the memory of the host device;

after the data is sent to the memory of the host device and in response to initiating an operation associated with the data, determining second parity information associated with the data; and

in response to the first parity information differing from the second parity information, terminating the operation,

wherein the data includes control information, and wherein the operation includes a non-blocking control sync operation to store the control information to a non-volatile memory while allowing updating of the control information during the storing of the control information.

11. The method of claim 10, wherein terminating the operation includes restarting the operation, rolling back the operation, declining to commit the operation, or invaliding data stored to a non-volatile memory of the data storage device in connection with the operation, and wherein the operation includes a relocation operation to copy the data from the memory of the host device to a non-volatile memory of the data storage device.

12. The method of claim 10, wherein the first parity information includes a first exclusive-or (XOR) value based on the data and determined by the controller at a first time, and wherein the second parity information includes a second XOR value based on the data and determined by the controller at a second time after the first time.

13. The method of claim 12, wherein the first XOR value differs from the second XOR value due to modification of the data by the host device between the first time and the second time.

14. An apparatus comprising:

means for sending data to a memory of a host device;

means for determining first parity information based on the data before the data is sent to the memory of the host device, and for determining, after the data is sent to the memory of the host device and in response to initiating an operation associated with the data, second parity information associated with the data; and

means for comparing the first parity information to the second parity information to enable termination of the operation in response to the first parity information differing from the second parity information,

wherein the data includes control information, and wherein the operation includes a non-blocking control sync operation to store the control information to a non-volatile memory while allowing updating of the control information during the storing of the control information.

15. The apparatus of claim 14, further comprising means for storing the first parity information.

16. A method of operation of a data storage device, the method comprising:

performing a first operation to store control information to a non-volatile memory of a data storage device;

performing a second operation to store data to a controller of the data storage device during the first operation, the data associated with at least a first logical block address (LBA); and

in response to determining that the first LBA is included in a range of LBAs associated with the first operation, selectively updating a first portion of the control information at the non-volatile memory,

wherein the first portion of the control information is updated independently of a second portion of the control information, wherein the first portion is associated with a first layer specified by a flash translation layer (FTL) of the data storage device, and wherein the second portion is associated with a second layer specified by the FTL.

17. The method of claim 16, wherein the first operation includes a non-blocking control sync (NBCS) operation to copy the control information from a memory of a host device to the non-volatile memory.

18. The method of claim 16, wherein the second operation is initiated in response to a request for write access to the non-volatile memory or in response to initiation of a maintenance operation at the data storage device.