Apparatuses and methods to control memory operations on buffers

• US 10,372,353 B2
• Filed: 05/31/2017
• Issued: 08/06/2019
• Est. Priority Date: 05/31/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Mohammadzadeh, Ali, Hoei, Jung Sheng, Srinivasan, Dheeraj, Grunzke, Terry M.
• Primary Examiner(s): Rossiter, Sean D
• Application Number:
  US15/609,569
• Publication Number:
  US 20180349029A1
• Time in Patent Office: 797 Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/601 Reconfiguration of cache memory
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The present disclosure relates to apparatuses and methods to control memory operations on buffers. An example apparatus includes a memory device and a host. The memory device includes a buffer and an array of memory cells, and the buffer includes a plurality of caches. The host includes a system controller, and the system controller is configured to control performance of a memory operation on data in the buffer. The memory operation is associated with data movement among the plurality of caches.

Claims

1. An apparatus, comprising:

a memory device including a buffer and an array of memory cells, wherein the buffer includes a plurality of caches; and

a host including a system controller, the system controller configured to control performance of a memory operation on data in the buffer, wherein the memory operation is associated with data movement among the plurality of caches, the system controller further configured to;

receive a request to issue a program suspend command associated with usage of a second cache while data are being programmed from the buffer to the array of memory cells;

issue a first command such that a first portion of the data is moved from the second cache to a cache of a plurality of first caches, wherein the first portion of the data is an amount of bits that are not programmed to the array of memory cells during the data being programmed to the array of memory cells; and

issue a second command that is the program suspend command such that an operation associated with the program suspend command is performed on the second cache while the first portion of the data is stored on the cache of the respective plurality of first caches.

2. The apparatus of claim 1, wherein the plurality of caches comprise:

a plurality of first caches coupled to a second cache; and

the second cache coupled to the host via an input/output (I/O) line.

3. The apparatus of claim 1, wherein the system controller is further configured to:

issue a third command such that the first portion of the data is moved from the cache of the respective plurality of first caches to the second cache;

issue a fourth command that is a program resume command; and

issue a fifth command such that the first portion of the data is programmed from the buffer to the array of memory cells.

4. The apparatus of claim 1, wherein a second portion of the data that is already programmed to the array of memory cells prior to the program suspend command being issued is not reprogrammed to the array of memory cells.

5. The apparatus of claim 1, wherein the system controller comprises a set features interface configured to issue a plurality of set feature commands to the memory device.

6. The apparatus of claim 1, wherein the system controller is further configured to perform a compute operation on data in the plurality of caches.

7. An apparatus, comprising:

a host configured to issue commands, wherein the host;

receives a request to issue a program suspend command while data is being programmed from the buffer to the array of memory cells;

issues a first command and a second command to the memory device responsive to the receipt of the request; and

a memory device including a buffer and an array of memory cells; and

wherein;

the memory device is configured to perform a memory operation on data in the buffer responsive to receipt of a command from the host;

the buffer includes a plurality of first caches coupled to a second cache and the second cache coupled to the host via an input/output (I/O) line; and

wherein the memory device is further configured to;

move a first portion of the data that is not programmed to the array of memory cells from the second cache of the buffer to a cache of the plurality of first caches responsive to receipt of the first command from the host and

move the first portion of the data from the cache of the plurality of first caches to the second cache of the buffer responsive to receipt of the second command that is issued from the host upon completion of an operation associated with the program suspend state.

8. The apparatus of claim 7, wherein the memory operation is performed on the data in the buffer during a program suspend state such that the plurality of first caches and the second cache of the buffer are available as a memory resource to the host.

9. The apparatus of claim 7, wherein an operation associated with the program suspend state is performed on the second cache of the buffer while the first portion of the data is stored in the cache of the plurality of first caches.

10. The apparatus of claim 7, wherein:

the memory device is further configured to program the first portion of the data from the buffer to the array of memory cells responsive to receipt of a third command that is issued from the host upon completion of the program suspend state; and

a second portion of the data that is, prior to the program suspend command being issued, already programmed to the array of memory cells is not reprogrammed to the array of memory cells.

11. The apparatus of claim 7, wherein the memory device is a NAND Flash memory.

12. The apparatus of claim 7, wherein the buffer is an internal buffer of the memory device.

13. A method, comprising:

receiving, from an external controller, a command to a memory device comprising an array of memory cells and a buffer, wherein the received command is a program suspend command and is associated with usage of a second cache while data are being programmed from the buffer to the array of memory cells;

issue a first command such that a first portion of the data is moved from the second cache to a cache of a plurality of first caches, wherein the first portion of the data is an amount of bits that are not programmed to the array of memory cells during the data being programmed to the array of memory cells;

issue a second command that is the program suspend command such that an operation associated with the program suspend command is performed on the second cache while the first portion of the data is stored on the cache of the respective plurality of first caches; and

responsive to receiving the command from the external controller, performing a memory operation on data in the buffer such that the buffer is available as a memory resource to the external controller;

wherein the external controller is located internal to a host such that the host is further configured to control performing the memory operation on the data in the buffer.

14. The method of claim 13, further comprising:

moving data stored on the buffer to the host such that a plurality of caches of the buffer is available to the external controller as the memory resource.

15. The method of claim 13, further comprising:

moving data stored on a second cache of the buffer to a first cache of the respective buffer such that the second cache of the buffer is available to the external controller as the memory resource.

16. The method of claim 13, wherein the memory operation further comprises an operation selected from:

resetting a plurality of caches of the buffer;

moving data among the plurality of caches of the buffer; and

swapping data stored on a first cache of the plurality of caches with other data stored on a second cache of the plurality of caches.

17. The method of claim 13, wherein the host is further configured to, via the external controller, control performing the memory operation on the data in the buffer independently respective to an internal controller of the memory device.

18. The method of claim 13, further comprising:

receiving a request to perform an operation associated with using a second cache of the buffer while programming data from the buffer to the array of memory cells;

storing a first portion of the data that is not programmed to the array of memory cells on a first cache of the buffer while performing the operation associated with using the second cache of the buffer; and

responsive to completing the operation, programming the portion of the data to the array of memory cells without reprogramming a second portion of the data that is already programmed to the array of memory cells.

19. The method of claim 13, further comprising:

programming data from the buffer to the array of memory cells; and

moving the data from the array of memory cells to the host via the buffer responsive to a failure event associated with programming the data to the array of memory cells.

20. An apparatus, comprising:

a memory device including a buffer and an array of memory cells, wherein the buffer includes a plurality of caches; and

a host including a system controller, the system controller configured to control performance of a memory operation on data in the buffer, wherein the memory operation is associated with data movement among the plurality of caches, the system controller further configured to;

issue a first command that is a program suspend command to initiate a program suspend state;

issue a second command during the program suspend state such that data is moved from a cache of a plurality of first caches to a second cache, and from the second cache to the system controller via a I/O line;

perform a read operation associated with usage of the second cache and the cache of the respective plurality of first caches; and

issue a third command upon completion of the read operation such that the data are moved from the host to the second cache and from the second cache to the cache of the respective plurality of first caches.

21. The apparatus of claim 20, wherein the system controller is further configured to move the data from the second cache to the cache of the respective plurality of first caches upon the completion of the read operation.

22. An apparatus, comprising:

a host configured to issue commands; and

a memory device including a buffer and an array of memory cells; and

wherein;

the memory device is configured to perform a memory operation on data in the buffer responsive to receipt of a command from the host;

the buffer includes a plurality of first caches coupled to a second cache and the second cache coupled to the host via an input/output (I/O) line, and wherein, responsive to receipt of the command from the host, the memory device is further configured to;

move data from the buffer to the host while in a program suspend state such that the second cache of the buffer and a cache of the plurality of first caches are available as a memory resource to the host;

perform a read operation associated with usage of the second cache of the buffer and the cache of the plurality of first caches while the data is stored on the host; and

move the data from the host to the buffer upon completion of the read operation.

23. The apparatus of claim 22, wherein the read operation comprises an operation selected from:

a soft-bit read operation

a corrected read operation;

a cache read operation; and

a channel calibration.