Processor for realizing at least two categories of functions

• US 10,372,359 B2
• Filed: 05/10/2017
• Issued: 08/06/2019
• Est. Priority Date: 05/10/2016
• Status: Active Grant

• Current Assignee: ChengDu HaiCun IP Technology LLC
• Original Assignee: ChengDu HaiCun IP Technology LLC
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Sain, Gautam
• Application Number:
  US15/591,205
• Publication Number:
  US 20170329548A1
• Time in Patent Office: 818 Days
• Field of Search: 711154
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 3/0617 in relation to availability
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G11C 17/10 in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices

Abstract

The present invention discloses a first preferred processor comprising a fixed look-up table circuit (LTC) and a writable LTC. The fixed LTC realizes at least a common function while the writable LTC realizes at least a non-common function. The present invention further discloses a second preferred processor comprising a two-dimensional (2-D) LTC and a three-dimensional (3-D) LTC. The 2-D LTC realizes at least a fast function while the 3-D LTC realizes at least a non-fast function.

Claims

1. A processor for realizing at least two categories of functions, comprising:

a printed memory array for storing at least a first portion of a first look-up table (LUT) for a first mathematical function, wherein data in said first LUT are physically written into said printed memory array during the manufacturing process of said printed memory array;

a writable memory array for storing at least a second portion of a second LUT for a second mathematical function, wherein data in said second LUT can be electrically written into said writable memory array after the manufacturing process of said writable memory array;

wherein said printed memory array and said writable memory array comprise physically different memory cells.

2. The processor according to claim 1, wherein said printed memory array is a two-dimensional (2-D) printed memory array.

3. The processor according to claim 1, wherein said printed memory array is a three-dimensional (3-D) printed memory array.

4. The processor according to claim 1, wherein said writable memory array is a 2-D writable memory array.

5. The processor according to claim 1, wherein said writable memory array is a 3-D writable memory array.

6. The processor according to claim 1, wherein data in said first LUT are physically written into said printed memory array using a printing method.

7. The processor according to claim 6, wherein said printing method includes photo-lithography, nano-imprint, e-beam lithography, DUV lithography, and laser programming.

8. The processor according to claim 1, wherein data in said second LUT are electrically written into said writable memory array using an electrical programming method.

9. The processor according to claim 1, wherein said writable memory array is an OTP memory array.

10. The processor according to claim 1, wherein said writable memory array is a re-programmable memory array.

11. A processor for realizing at least two categories of functions, comprising:

a semiconductor substrate;

a two-dimensional (2-D) memory array on said semiconductor substrate for storing at least a third portion of a third look-up table (LUT) for a third mathematical function;

a three-dimensional (3-D) memory array above said semiconductor substrate for storing at least a fourth portion of a fourth LUT for a fourth mathematical function;

wherein said 2-D memory array and said 3-D memory array are located on different physical levels.

12. The processor according to claim 11, wherein 2-D memory array is a first printed memory array;

and, said 3-D memory array is a second printed memory array.

13. The processor according to claim 11, wherein 2-D memory array is a printed memory array;

and, said 3-D memory array is a writable memory array.

14. The processor according to claim 11, wherein 2-D memory array is a writable memory array;

and, said 3-D memory array is a printed memory array.

15. The processor according to claim 11, wherein 2-D memory array is a first writable memory array;

and, said 3-D memory array is a second writable memory array.

16. The processor according to claim 11, wherein said 2-D memory array is faster than said 3-D memory array.

17. The processor according to claim 11, wherein said 3-D memory array has a lower storage cost than said 2-D memory array.

18. The processor according to claim 11, wherein said 3-D memory array at least partially covers said 2-D memory array.

19. The processor according to claim 11, further comprising an arithmetic logic circuit (ALC) on said semiconductor substrate for performing arithmetic operations on selected data from said third or fourth LUT.

20. The processor according to claim 19, wherein said 3-D memory array is stacked above said ALC.