Memory controller, memory system, and control method
First Claim
Patent Images
1. A memory controller comprising:
- a memory interface that is connectable to a nonvolatile memory that includes a plurality of memory cells;
a memory including a mode management table indicating, as an operation mode for a group of memory cells including a first memory cell, an n-bit mode (where n is 2 or more) or an m-bit mode (where m is less than n); and
a processor configured to;
during a write operation,control the memory interface to perform writing of data that has a first number of bits to the first memory cell in the n-bit mode, when the mode management table indicates the n-bit mode as the operation mode, andoperate to convert data that has a second number of bits less than the first number into data that has the first number of bits by addition of dummy data and control the memory interface to perform writing of the converted data to the first memory cell in the n-bit mode, when the mode management table indicates the m-bit mode as the operation mode, andduring a read operation,control the memory interface to perform reading of data in the first memory cell in the m-bit mode, when the mode management table indicates the m-bit mode as the operation mode.
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Abstract
A memory controller includes a memory interface that is connected to a non-volatile memory that includes a plurality of memory cells, and a control unit. The control unit controls the memory interface to perform writing of data that has a first number of bits to a first memory cell in an n-bit write mode (where n is 2 or more), and when performing reading of the data written into the first memory cell, to control the memory interface to perform reading of data in an m-bit read mode (where m is less than n), as a result of which data that has a second number of bits which is smaller than the first number of bits, is returned from the first memory cell.
24 Citations
16 Claims
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1. A memory controller comprising:
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a memory interface that is connectable to a nonvolatile memory that includes a plurality of memory cells; a memory including a mode management table indicating, as an operation mode for a group of memory cells including a first memory cell, an n-bit mode (where n is 2 or more) or an m-bit mode (where m is less than n); and a processor configured to; during a write operation, control the memory interface to perform writing of data that has a first number of bits to the first memory cell in the n-bit mode, when the mode management table indicates the n-bit mode as the operation mode, and operate to convert data that has a second number of bits less than the first number into data that has the first number of bits by addition of dummy data and control the memory interface to perform writing of the converted data to the first memory cell in the n-bit mode, when the mode management table indicates the m-bit mode as the operation mode, and during a read operation, control the memory interface to perform reading of data in the first memory cell in the m-bit mode, when the mode management table indicates the m-bit mode as the operation mode. - View Dependent Claims (2, 3, 4, 5, 6, 8, 9, 10, 11)
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7. A method of performing read and write operations on a nonvolatile memory that includes a plurality of memory cells, said method comprising:
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during a write operation, performing writing of data that has a first number of bits to a first memory cell in an n-bit mode (where n is 2 or more), when a mode management table indicating, as an operation mode for a group of memory cells including the first memory cell, the n-bit mode; and converting data that has a second number of bits less than the first number into data that has the first number of bits by adding dummy data, and performing writing of the converted data to the first memory cell in the n-bit mode, when the mode management table indicates, as the operation mode, an m-bit mode (where m is less than n); and during a read operation, performing reading of data in the first memory cell in the m-bit mode, when the mode management table indicates the m-bit mode as the operation mode. - View Dependent Claims (15, 16)
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12. A memory system comprising:
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a nonvolatile memory that includes a plurality of memory cells; and a memory controller including; a memory interface connectable to the nonvolatile memory; a memory including a mode management table indicating, as an operation mode for a group of memory cells including a first memory cell, an n-bit mode (where n is 2 or more) or an m-bit mode (where m is less than n); and a processor configured to; during a write operation, control the memory interface to perform writing of data that has a first number of bits to the first memory cell in the n-bit mode, when the mode management table indicates the n-bit mode as the operation mode, and operate to convert data that has a second number of bits less than the first number into data that has the first number of bits by addition of dummy data and control the memory interface to perform writing of the converted data to the first memory cell in the n-bit mode, when the mode management table indicates the m-bit mode as the operation mode, and during a read operation, control the memory interface to perform reading of data in the first memory cell in the m-bit mode, when the mode management table indicates the m-bit mode as the operation mode. - View Dependent Claims (13, 14)
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Specification