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Compute architecture in a memory device of distributed computing system

  • US 10,372,506 B2
  • Filed: 11/09/2016
  • Issued: 08/06/2019
  • Est. Priority Date: 12/12/2011
  • Status: Active Grant
First Claim
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1. A method performed by a processing module embedded in a solid state memory device, the method comprising:

  • receiving, at the processing module, at least one partial task related to a group of slices of contiguous data;

    receiving, at the solid state memory device, slices of the group of slices of contiguous data to produce received slices;

    random access storing received slices in the solid state memory device, using the processing module;

    determining, by the processing module, whether to execute the at least one partial task;

    in response to a positive determination;

    random access retrieving, by the processing module, a portion of the-received slices from the solid state memory device;

    executing, by the processing module, the at least one partial task using the portion of the received slices to generate a partial result;

    random access storing, by the processing module, the partial result in the same solid state memory device used to store the received slices;

    dispersed storage error encoding the partial result to produce a plurality of sets of dispersed error encoded slices; and

    facilitating, by the processing module, dispersed storage of the plurality of sets of dispersed error encoded slices in a distributed storage task network (DSTN).

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