Memory array and measuring and testing methods for inter-hamming differences of memory array

• US 10,372,532 B2
• Filed: 08/15/2017
• Issued: 08/06/2019
• Est. Priority Date: 12/07/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lu, Shih-Lien Linus, Li, Kun-Hsi, Adham, Saman M. I.
• Primary Examiner(s): Tabone, Jr., John J
• Application Number:
  US15/677,414
• Publication Number:
  US 20180157555A1
• Time in Patent Office: 721 Days
• Field of Search: 714777, 714763, 714768, 714773
• CPC Class Codes: G01N 2035/00782 reprogrammmable code
• CPC Class Codes: G01N 35/00594 Quality control, including calibration or testing of components of the analyser
• CPC Class Codes: G01N 35/00732 Identification of carriers, materials or components in automatic analysers
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: H03M 13/1575 Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes

Abstract

A memory device is provided. The memory device includes a memory array including a plurality of sections, and an inter-hamming difference analyzer. Each section includes a plurality of bits, and the numbers of the bits of the plurality of sections are the same. The inter-hamming difference analyzer is configured to obtain contents of the plurality of sections operating in different operating conditions, to obtain a plurality of inter-hamming differences of the contents, and to provide a maximum inter-hamming difference and a minimum inter-hamming difference among the inter-hamming differences of the plurality of sections. The inter-hamming difference represents the number of unlike bits between the content of one section corresponding to a first operating condition and the content of another section corresponding to a second operating condition that is different from the first operating condition.

Claims

1. A memory device, comprising:

a memory array comprising a plurality of sections, wherein each section of the plurality of sections comprises a plurality of bits, and the numbers of the bits of the plurality of sections are the same; and

an inter-hamming difference analyzer configured to obtain contents of the plurality of sections operating in different operating conditions, to obtain a plurality of inter-hamming differences of the contents, and to provide a maximum inter-hamming difference and a minimum inter-hamming difference among the inter-hamming differences of the plurality of sections,

wherein the inter-hamming difference represents the number of unlike bits between the content of one section of the plurality of sections corresponding to a first operating condition and the content of another section of the plurality of sections corresponding to a second operating condition that is different from the first operating condition.

2. The memory device as claimed in claim 1, wherein the inter-hamming difference analyzer comprises:

a storage device configured to store the contents of the plurality of sections corresponding to the first operating condition; and

a comparator configured to determine the hamming differences between the content of a first section of the plurality of sections corresponding to the second operating condition and the contents of a plurality of sections other than the first section stored in the storage device.

3. The memory device as claimed in claim 2, wherein the storage device has the same capacity as the memory array.

4. The memory device as claimed in claim 3, wherein when the inter-hamming difference analyzer obtains a first content of the first section from the memory array operating in the second operating condition, the comparator determines the inter-hamming differences between the first content of the first section from the memory array and the contents of the plurality of sections except the first section from the storage device, wherein the number of inter-hamming differences is equal to the number of sections of the memory array minus one.

5. The memory device as claimed in claim 1, wherein the section of the memory array has an individual location in the memory array, and the inter-hamming difference analyzer determines the inter-hamming difference between a first content of a first section of the plurality of sections corresponding to the first operating condition and a second content of a second section of the plurality of sections corresponding to the second operating condition, wherein the first section and the second section have different locations in the memory array.

6. The memory device as claimed in claim 5, wherein when the determined inter-hamming difference is greater than the maximum inter-hamming difference, the inter-hamming difference analyzer assigns the determined inter-hamming difference as the maximum inter-hamming difference, and when the determined inter-hamming difference is less than the minimum inter-hamming difference, the inter-hamming difference analyzer assigns the determined inter-hamming difference as the minimum inter-hamming difference.

7. The memory device as claimed in claim 1, wherein power supplies, operation frequencies or operation temperatures of the first and second operating conditions are different.

8. The memory device as claimed in claim 1, wherein when the number of sections of the memory array is N, and the number of inter-hamming differences of the contents of the plurality of sections between the first and second operating conditions is N×

(N−

1).

9. A method for measuring inter-hamming difference of a memory array divided into a plurality of sections, comprising:

obtaining a plurality of first contents of the plurality of sections from the memory array when the memory array is operating in a first operating condition;

obtaining a plurality of second contents of the plurality of sections from the memory array when the memory array is operating in a second operating condition, wherein power supplies, operation frequencies or operation temperatures of the first and second operating conditions are different;

obtaining a plurality of inter-hamming differences between the first and second contents, wherein the inter-hamming difference represents the number of unlike bits between the first content of one section of the plurality of sections and the second content of another section of the plurality of sections; and

obtaining an inter-hamming difference range according to a maximum inter-hamming difference and a minimum inter-hamming difference among the inter-hamming differences.

10. The method as claimed in claim 9, further comprising:

obtaining a test result of the memory array according to the inter-hamming difference range and an intra-hamming difference range.

11. The method as claimed in claim 9, further comprising:

storing the first contents of the plurality of sections from the memory array into a storage device having the same capacity as the memory array.

12. The method as claimed in claim 9, wherein obtaining the inter-hamming differences between the first and second contents further comprises:

according to the first content of a first section of the plurality of sections corresponding to the first operating condition, determining the inter-hamming differences between the first content of the first section and the second contents of the plurality of sections except for the first section corresponding to the second operating condition,

wherein the number of inter-hamming differences corresponding to the first content is equal to the number of sections of the memory array minus one.

13. The method as claimed in claim 9, wherein the section has an individual location in the memory array, and obtaining the inter-hamming differences between the first and second contents further comprises:

determining the inter-hamming difference between the first content of a first section of the plurality of sections corresponding to the first operating condition and the second content of a second section of the plurality of sections corresponding to the second operating condition,

wherein the first section and the second section have different locations in the memory array.

14. The method as claimed in claim 13, further comprising:

assigning the determined inter-hamming difference as the maximum inter-hamming difference when the determined inter-hamming difference is greater than the maximum inter-hamming difference; and

assigning the determined inter-hamming difference as the minimum inter-hamming difference when the determined inter-hamming difference is less than the minimum inter-hamming difference.

15. The method as claimed in claim 9, wherein when the number of sections of the memory array is N, and the number of inter-hamming differences of the contents of the plurality of sections between the first and second operating conditions is N×

(N−

1).

16. A method for testing a memory array divided into a plurality of sections, comprising:

applying a first operating condition to the memory array, and obtaining a plurality of first contents of the plurality of sections from the memory array operating in the first operating condition;

after storing the first contents, applying a second operating condition to the memory array, and obtaining a plurality of second contents of the plurality of sections from the memory array operating in the second operating condition;

obtaining a plurality of inter-hamming differences between the stored first contents and the second contents, wherein the inter-hamming difference represents the number of unlike bits between the stored first content of one section of the plurality of sections and the second content of another section of the plurality of sections; and

obtaining a test result of the memory array according to a maximum inter-hamming difference and a minimum inter-hamming difference among the inter-hamming differences.

17. The method as claimed in claim 16, wherein obtaining the inter-hamming differences between the stored first contents and the second contents further comprises:

according to the stored first content of a first section corresponding to the first operating condition, determining the inter-hamming differences between the stored first content of the first section and the second contents of the plurality of sections except for the first section corresponding to the second operating condition,

wherein the number of inter-hamming differences corresponding to the first content is equal to the number of sections of the memory array minus one.

18. The method as claimed in claim 16, wherein the section has an individual location in the memory array, and obtaining the inter-hamming differences between the stored first contents and the second contents further comprises:

determining the inter-hamming difference between the stored first content of a first section corresponding to the first operating condition and the second content of a second section corresponding to the second operating condition,

wherein the first section and the second section have different locations in the memory array.

19. The method as claimed in claim 18, further comprising:

assigning the determined inter-hamming difference as the maximum inter-hamming difference when the determined inter-hamming difference is greater than the maximum inter-hamming difference; and

assigning the determined inter-hamming difference as the minimum inter-hamming difference when the determined inter-hamming difference is less than the minimum inter-hamming difference.

20. The method as claimed in claim 16, wherein when the number of sections of the memory array is N, and the number of inter-hamming differences of the contents of the plurality of sections between the first and second operating conditions is N×

(N−

1).