Methods and apparatus for aggregating packet transfer over a virtual bus interface

• US 10,372,637 B2
• Filed: 09/29/2017
• Issued: 08/06/2019
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Pulyala, Radha Kumar, Garg, Saurabh, Sanghi, Karan
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): Modo, Ronald T
• Application Number:
  US15/721,485
• Publication Number:
  US 20180089118A1
• Time in Patent Office: 676 Days
• CPC Class Codes: G06F 13/287 Multiplexed DMA G06F13/30 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments are configured to: (i) multiplex multiple logical interfaces over a single physical interface, (ii) exchange session management and logical interface control, (iii) manage flow control, (iv) provide “hints” about the data (e.g., metadata), and/or (v) pad data packets. In one particular implementation, the methods and apparatus are configured for use within a wireless-enabled portable electronic device, such as for example a cellular-enabled smartphone, and make use of one or more features of a high-speed serialized physical bus interface.

Claims

1. Processor apparatus, comprising:

a first digital processor apparatus;

a physical bus interface in data communication with the first digital processor apparatus; and

a non-transitory computer-readable medium comprising computer-readable instructions, the computer-readable instructions being configured to, when executed by the first digital processor apparatus, cause the processor apparatus to;

receive an aggregated data block and an associated aggregated command block;

divide the aggregated command block into a first constituent command block and a second constituent command block, the first constituent command block being configured to reference the second constituent command block;

divide the aggregated data block into a plurality of datagrams based on the first and second constituent command blocks; and

provide the plurality of datagrams to corresponding ones of a plurality of data interfaces.

2. The processor apparatus of claim 1, wherein the aggregated data block comprises one or more Internet Protocol (IP) datagrams.

3. The processor apparatus of claim 2, wherein the computer-readable instructions are configured to, when executed by the first digital processor apparatus, cause the first digital processor apparatus to order at least a subset of the plurality of datagrams into a session, the session associated with one data interface.

4. The processor apparatus of claim 1, wherein the computer-readable instructions are configured to, when executed by the first digital processor apparatus, cause the first digital processor apparatus to identify when a constituent command block is missing or corrupted, and responsively request a retransmission of the constituent command block.

5. The processor apparatus of claim 1, wherein the computer-readable instructions are configured to, when executed by the first digital processor apparatus, cause the first digital processor apparatus to identify when a constituent command block is missing or corrupted, and responsively flag an error.

6. The processor apparatus of claim 1, wherein the computer-readable instructions are configured to, when executed by the first digital processor apparatus, cause the first digital processor apparatus to:

separately queue one or more aggregated data blocks and one or more aggregated command blocks; and

identify the aggregated data block and the associated aggregated command block based on a sequence number associated therewith.

7. The processor apparatus of claim 1, wherein the computer-readable instructions are configured to, when executed by the first digital processor apparatus, cause the first digital processor apparatus to:

generate a session from the plurality of datagrams;

store the session within a receive buffer; and

indicate when the receive buffer has an overflow or under-flow condition.

8. A method of demultiplexing one or more aggregated data into a plurality of data structures, comprising:

receiving an aggregated data block and an associated aggregated command block;

dividing the aggregated command block into a plurality of different constituent command blocks;

dividing the aggregated data block into a plurality of datagrams based on the plurality of different constituent command blocks; and

generating a session from the plurality of datagrams.

9. The method of claim 8, further comprising identifying when one of the plurality of constituent command blocks is missing or corrupted, and responsively requesting a retransmission of the one constituent command block.

10. The method of claim 8, further comprising identifying when one of the plurality of constituent command blocks is missing or corrupted, and responsively flagging an error.

11. The method of claim 8, further comprising separately queuing one or more aggregated data blocks and one or more aggregated command blocks;

and

identifying the aggregated data block and the associated aggregated command block based on a sequence number associated therewith.

12. The method of claim 8, further comprising storing the session within a receive buffer.

13. The method of claim 12, further comprising indicating when the receive buffer may have a future overflow or under-flow condition.

14. The method of claim 8, wherein the generated session is based on stateful information associated with a previous aggregated command block.

15. A processor apparatus configured to:

receive an aggregated data block and an aggregated command block associated with the aggregated data block;

divide the aggregated command block into a plurality of constituent command blocks, the plurality of constituent command blocks comprising a linked list of commands;

divide the aggregated data block into a plurality of datagrams based on the plurality of constituent command blocks comprising the linked list of commands, the plurality of datagrams comprising a linked list of datagrams;

provide the plurality of datagrams to corresponding ones of a plurality of data interfaces.

16. The processor apparatus of claim 15, wherein the processor apparatus is further configured to order a subset of the plurality of datagrams into a session, the session associated with one data interface.

17. The processor apparatus of claim 15, wherein the processor apparatus is further configured to identify when one of the plurality of constituent command blocks is missing or corrupted, and responsively request a retransmission of the one command block.

18. The processor apparatus of claim 15, wherein the processor apparatus is further configured to identify when one of the plurality of constituent command blocks is missing or corrupted, and responsively flag an error.

19. The processor apparatus of claim 15, wherein the processor apparatus is further configured to:

separately queue one or more aggregated data blocks and one or more aggregated command blocks; and

identify the aggregated data block and the associated aggregated command block based on a sequence number associated therewith.

20. The processor apparatus of claim 15, wherein the processor apparatus is further configured to:

generate a session from the plurality of datagrams;

store the session within a receive buffer; and

indicate when the receive buffer has an overflow or under-flow condition.