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Methods and apparatus for aggregating packet transfer over a virtual bus interface

  • US 10,372,637 B2
  • Filed: 09/29/2017
  • Issued: 08/06/2019
  • Est. Priority Date: 09/16/2014
  • Status: Active Grant
First Claim
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1. Processor apparatus, comprising:

  • a first digital processor apparatus;

    a physical bus interface in data communication with the first digital processor apparatus; and

    a non-transitory computer-readable medium comprising computer-readable instructions, the computer-readable instructions being configured to, when executed by the first digital processor apparatus, cause the processor apparatus to;

    receive an aggregated data block and an associated aggregated command block;

    divide the aggregated command block into a first constituent command block and a second constituent command block, the first constituent command block being configured to reference the second constituent command block;

    divide the aggregated data block into a plurality of datagrams based on the first and second constituent command blocks; and

    provide the plurality of datagrams to corresponding ones of a plurality of data interfaces.

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