Multi-processor device

• US 10,372,654 B2
• Filed: 01/25/2017
• Issued: 08/06/2019
• Est. Priority Date: 01/22/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Ishimi, Koichi
• Primary Examiner(s): Zaman, Faisal M
• Application Number:
  US15/415,079
• Publication Number:
  US 20170132167A1
• Time in Patent Office: 923 Days
• Field of Search: 710306, 361783, 36167932, 361760
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4031 with arbitration
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.

Claims

1. A semiconductor device comprising:

a semiconductor chip with four sides and, in plan view, having;

a first edge extending in a first direction,

a second edge extending in a second direction crossing the first direction,

a third edge opposite the second edge and extending in the second direction, and

a fourth edge opposite the first edge and extending in the first direction;

a first type processor formed on the semiconductor chip;

a second type processor formed on the semiconductor chip;

a first external bus interface coupled to the first type processor through a first bus; and

a second external bus interface coupled to the second type processor through a second bus,

wherein the first type processor operates at a first operating speed greater than a second operating speed of the second type processor,

wherein, in plan view, the first type processor is located closer to the first edge than the fourth edge, and located closer to the first edge than both the first external bus interface and the second external bus interface,

wherein, in plan view, the first external bus interface is located closer to the second edge than the third edge, and having a portion located closer to the fourth edge than the first edge,

wherein, in plan view, the second external bus interface is located closer to the third edge than the second edge, and having a portion located closer to the fourth edge than the first edge,

wherein the first type processor has access to both the first external bus interface and the second external bus interface, and the second type processor and elements coupled to the second bus have access to the second external bus interface and do not have access to the first external bus interface.

2. The semiconductor device according to claim 1, the semiconductor device further comprising:

a cache that is coupled to the first bus and the second bus, the cache being disposed between the first bus and the second bus.

3. The semiconductor device according to claim 2, wherein the cache is a secondary cache.

4. The semiconductor device according to claim 1, the semiconductor device further comprising:

a cache and a bus bridge,

wherein the first type processor accesses the first external bus interface through the cache, and accesses the second external bus interface through the bus bridge.

5. The semiconductor device according to claim 1, wherein the second type processor is a SIMD type processor.

6. The semiconductor device according to claim 1,

wherein, in plan view, a first area in which the first type processor is located has closely spaced voltage supply lines, and

wherein, in plan view, a second area in which the second type processor is located has spaced voltage supply lines.

7. The semiconductor device according to claim 6, wherein a number of voltage supply terminals in the first area is larger than a number of voltage supply terminals in the second area.

8. The semiconductor device according to claim 1, wherein each of the first and second external bus interfaces is a DRAM interface.

9. The semiconductor device according to claim 8, wherein the first external bus interface is a Double-Data-Rate DRAM memory interface.

10. The semiconductor device according to claim 1, wherein the first bus and the first external bus interface operate at the same clock frequency to each other.

11. The semiconductor device according to claim 10, wherein the second bus and the second external bus interface operate at the same clock frequency to each other.

12. The semiconductor device according to claim 1, wherein the second bus and the second external bus interface operate at the same clock frequency to each other.