Memory-mapped state bus for integrated circuit
First Claim
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1. A system comprising:
- an integrated circuit comprising data utilization circuitry, wherein the data utilization circuitry comprises;
a plurality of logic blocks; and
a broadcast bus coupled to the plurality of logic blocks, wherein the broadcast bus is configured to broadcast an addressed message to each logic block of the plurality of logic blocks; and
a configurator device comprising one or more processors configured to;
receive a logic design for the plurality of logic blocks;
based at least in part on the logic design, assign logic block addresses to the plurality of logic blocks such that logic blocks of the plurality of logic blocks are balanced along the broadcast bus, wherein each logic block of the plurality of logic blocks disposed on a first side of the broadcast bus corresponds to a respective logic block of the plurality of logic blocks disposed on a second side of the broadcast bus; and
program the logic design into the integrated circuit.
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Abstract
Systems and devices are provided for broadcasting a message to addressed logic blocks in lieu of, or in addition to, programming individual status registers of an integrated circuit. One such device may be an integrated circuit that includes a broadcast bus and addressed logic blocks. The broadcast bus may broadcast an addressed message that includes content and a target address. Each of the addressed logic blocks may receive the addressed message from the broadcast bus and use the content of the addressed message only when the target address matches an address assigned to that logic block.
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Citations
19 Claims
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1. A system comprising:
an integrated circuit comprising data utilization circuitry, wherein the data utilization circuitry comprises; a plurality of logic blocks; and a broadcast bus coupled to the plurality of logic blocks, wherein the broadcast bus is configured to broadcast an addressed message to each logic block of the plurality of logic blocks; and a configurator device comprising one or more processors configured to; receive a logic design for the plurality of logic blocks; based at least in part on the logic design, assign logic block addresses to the plurality of logic blocks such that logic blocks of the plurality of logic blocks are balanced along the broadcast bus, wherein each logic block of the plurality of logic blocks disposed on a first side of the broadcast bus corresponds to a respective logic block of the plurality of logic blocks disposed on a second side of the broadcast bus; and program the logic design into the integrated circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit comprising:
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a broadcast bus configured to broadcast an addressed message comprising content and a target address, wherein the broadcast bus comprises a plurality of addressed logic blocks coupled to the broadcast bus wherein the plurality of addressed logic blocks are balanced along the broadcast bus, wherein each addressed logic block of the plurality of addressed logic blocks disposed on a first side of the broadcast bus corresponds to a respective addressed logic block of the plurality of addressed logic blocks disposed on a second side of the broadcast bus. - View Dependent Claims (11, 12)
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13. A method comprising:
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receiving, via one or more processors, a logic design for programmable fabric of a programmable logic device, wherein logic blocks of the programmable fabric are accessible by a hardware broadcast bus; based at least in part on the logic design, assigning, via the one or more processors, logic block addresses to logic blocks such that logic blocks are balanced along the hardware broadcast bus, wherein each logic block of the plurality of logic blocks disposed on a first side of the broadcast bus corresponds to a respective logic block of the plurality of logic blocks disposed on a second side of the broadcast bus; and programming, via the one or more processors, the logic design into the programmable logic device. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification