Multiphase data receiver with distributed DFE

• US 10,372,665 B2
• Filed: 10/24/2017
• Issued: 08/06/2019
• Est. Priority Date: 10/24/2016
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin
• Primary Examiner(s): Neff, Michael R
• Application Number:
  US15/792,599
• Publication Number:
  US 20180113835A1
• Time in Patent Office: 651 Days
• Field of Search: 375233
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: H04L 2025/03579 Modifying the tap spacing
• CPC Class Codes: H04L 2025/03777 characterised by the signalling
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03267 with decision feedback equalisers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and systems are described for receiving an input data voltage signal at a first data decision circuit of set of pipelined data decision circuits, receiving an aggregate decision feedback equalization (DFE) correction current signal from a first analog current summation bus, the aggregate DFE correction current signal comprising a plurality of DFE tap-weighted currents from respective other data decision circuits of the set of pipelined data decision circuits, determining a data output decision value based on the received input data voltage signal and the received aggregate DFE correction current signal, and generating at least one outbound DFE tap-weighted current on at least one other analog current summation bus connected to at least one other data decision circuit of the set of pipelined data decision circuits.

Claims

1. A method comprising:

receiving an input data voltage signal at a first data decision circuit of a set of pipelined data decision circuits operating in parallel in a respective set of signal processing phases, each data decision circuit of the set of pipelined data decision circuits operating on a respective phase of a plurality of phases of a sampling clock;

receiving an aggregate decision feedback equalization (DFE) correction current signal from a first analog current summation bus, the aggregate DFE correction current signal comprising at least one DFE tap-weighted current from at least one other respective data decision circuits of the set of pipelined data decision circuits;

determining a data output decision value based on the received input data voltage signal and the received aggregate DFE correction current signal; and

,

generating at least one outbound DFE tap-weighted current on at least one other analog current summation bus connected to at least one other data decision circuit of the set of pipelined data decision circuits.

2. The method of claim 1, further comprising generating the at least one DFE tap-weighted current using at least one differential pair of transistors connected in parallel to the first analog summation bus.

3. The method of claim 2, wherein each DFE tap-weighted current has a corresponding magnitude determined by a corresponding DFE correction factor current source connected to a respective differential pair of transistors.

4. The method of claim 2, wherein each DFE tap-weighted current has a sign determined by a historical decision generated by an associated data decision circuit.

5. The method of claim 2, wherein the at least one DFE tap-weighted current is drawn through a current buffer connected to the at least one differential pair of transistors.

6. The method of claim 1, wherein the aggregate DFE correction current signal further comprises at least one DFE tap-weighted current provided by a data decision history element.

7. The method of claim 1, wherein determining the data output decision value comprises combining the received input data voltage with the aggregate DFE correction current signal.

8. The method of claim 7, wherein combining the received input data voltage with the aggregate DFE correction current signal comprises generating a data current signal representative of the received input data voltage and performing an analog current summation of the aggregate DFE correction current signal and the data current signal.

9. The method of claim 8, wherein generating the data current signal comprises applying the input data voltage to a differential pair of transistors to draw the data current through a pair of resistors connected to the first analog current summation bus.

10. An apparatus comprising:

a set of pipelined data decision circuits interconnected by a distributed analog current summation bus, the set of pipelined data decision circuits operating in parallel in a respective set of signal processing phases, each data decision circuit of the set of pipelined data decision circuits operating on a respective phase of a plurality of phases of a sampling clock, the set of pipelined data decision circuits comprising a first data decision circuit configured to;

receive (i) an input data voltage signal and (ii) an aggregate decision feedback equalization (DFE) correction current signal from a first analog current summation bus of the distributed analog current summation bus, the aggregate DFE correction current signal comprising at least one DFE tap-weighted current from respective other data decision circuits of the set of pipelined data decision circuits;

determine a data output decision value based on the received input data voltage signal and the received aggregate DFE correction current signal; and

,

generate at least one DFE tap-weighted current on at least one other analog current summation bus connected to at least one other data decision circuit of the set of pipelined data decision circuits.

11. The apparatus of claim 10, wherein each of the respective other data decision circuits comprises a respective differential pair connected to the first analog current summation bus for generating a corresponding DFE tap-weighted current of the at least one DFE tap-weighted currents.

12. The apparatus of claim 11, wherein the respective differential pair is configured to receive a corresponding historical data decision generated by a corresponding other data decision circuit to apply a sign to the corresponding DFE tap-weighted current.

13. The apparatus of claim 11, wherein the respective differential pair is connected to a DFE correction factor current source configured to apply a magnitude to the corresponding DFE tap-weighted current.

14. The apparatus of claim 10, further comprising a current buffer connected between the first analog current summation bus and the first data decision circuit.

15. The apparatus of claim 10, further comprising a data decision history element configured to provide additional DFE tap-weighted currents to the first analog current summation bus.

16. The apparatus of claim 10, wherein the data output decision value is determined based on a combination of the received input data voltage with the aggregate DFE correction current signal at a differential output node.

17. The apparatus of claim 16, further comprising a pair of resistors configured to generate a combined output voltage by drawing a data current signal representative of the received input data voltage and the aggregate DFE correction current signal through the pair of resistors.

18. The apparatus of claim 17, further comprising an input differential pair of transistors connected to the differential output node and configured to receive the input data voltage and to responsively generate the data current signal.