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Content addressable memory device having electrically floating body transistor

  • US 10,373,685 B2
  • Filed: 06/20/2018
  • Issued: 08/06/2019
  • Est. Priority Date: 01/14/2013
  • Status: Active Grant
First Claim
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1. A content addressable memory array comprising a plurality of content addressable memory cells arranged in a plurality of rows and columns, wherein each said content addressable memory cell comprises:

  • a first floating body transistor;

    a second floating body transistor; and

    a third transistor;

    wherein said first floating body transistor and said second floating body transistor are electrically connected in series through a common node;

    wherein said third transistor is electrically connected to said common node; and

    wherein said first floating body transistor and said second floating body transistor store complementary data.

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