Contacts formed with self-aligned cuts

• US 10,373,875 B1
• Filed: 03/22/2018
• Issued: 08/06/2019
• Est. Priority Date: 03/22/2018
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Jaeger, Daniel, Park, Chanro, Economikos, Laertis, Wang, Haiting, Zang, Hui
• Primary Examiner(s): Ahmed, Shahed
• Application Number:
  US15/928,783
• Time in Patent Office: 502 Days
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. In one process, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. In another process, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.

Claims

1. A method comprising:

forming a first source/drain region and a second source/drain region adjacent to a temporary gate structure;

forming a sacrificial layer over the first source/drain region and the second source/drain region;

etching a trench in the sacrificial layer that is disposed between the first source/drain region and the second source/drain region;

depositing a first dielectric material in the trench to form a dielectric pillar between the first source/drain region and the second source/drain region;

after depositing the first dielectric material in the trench, forming a fill layer over the first source/drain region and the second source/drain region;

after forming the fill layer, replacing the temporary gate structure with a functional gate structure;

after replacing the temporary gate structure with the functional gate structure, removing the fill layer; and

forming a conductive layer having a first portion contacting the first source/drain region and a second portion contacting the second source/drain region,

wherein the dielectric pillar separates the first portion of the conductive layer from the second portion of the conductive layer.

2. The method of claim 1 wherein the sacrificial layer is composed of an organic planarization layer material.

3. The method of claim 1 further comprising:

before depositing the first dielectric material in the trench, depositing a dielectric liner on sidewalls of the trench.

4. The method of claim 1 wherein etching the trench in the sacrificial layer comprises:

forming a lithography stack over the sacrificial layer;

forming an opening in the lithography stack to expose a portion of the sacrificial layer; and

etching the exposed portion of the sacrificial layer.

5. The method of claim 1 wherein etching the trench in the sacrificial layer comprises:

etching an upper portion of the trench in the sacrificial layer, the upper portion exposing a portion of the first source/drain region and a portion of the second source/drain region;

forming a dielectric spacer on sidewalls of the upper portion of the trench; and

etching a lower portion of the trench in the sacrificial layer, the dielectric liner material protecting remaining portions of the sacrificial layer arranged over the first source/drain region and the second source/drain region.

6. The method of claim 5 wherein etching the lower portion of the trench comprises:

anisotropically etching the sacrificial layer disposed between the first source/drain region and the second source/drain region; and

isotropically etching the sacrificial layer disposed below the portion of the first source/drain region and below the portion of the second source/drain region.

7. The method of claim 5 further comprising:

depositing a dielectric liner on sidewalls of the lower portion of the trench, on the exposed portion of the first source/drain region, and on the exposed portion of the second source/drain region.

8. The method of claim 7 wherein the dielectric liner and the dielectric spacer are each composed of a second dielectric material.

9. The method of claim 5 further comprising:

before forming the dielectric spacer, etching an outer portion of the first source/drain region and an outer portion of the second source/drain region.