Embedded bridge with through-silicon vias

• US 10,373,893 B2
• Filed: 06/30/2017
• Issued: 08/06/2019
• Est. Priority Date: 06/30/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Vaidya, Aditya S., Mahajan, Ravindranath V., Raorane, Digvijay A., Start, Paul R.
• Primary Examiner(s): Hargrove, Frederick B
• Application Number:
  US15/640,406
• Publication Number:
  US 20190006264A1
• Time in Patent Office: 767 Days
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/1703 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/09 of a plurality of bonding areas
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias

Abstract

An integrated circuit (IC) package including a substrate comprising a dielectric, and at least one bridge die embedded in the first dielectric. The embedded bridge die comprises a plurality of through-vias extending from a first side to a second side and a first plurality of pads on the first side and a second plurality of pads on the second side. The first plurality of pads are interconnected to the second plurality of pads by the plurality of through-vias extending vertically through the bridge die. The second plurality of pads is coupled to a buried conductive layer in the substrate by solder joints or by an adhesive conductive film between the second plurality of pads of the bridge die and conductive structures in the buried conductive layer, and wherein the adhesive conductive film is over a second dielectric layer on the bridge die.

Claims

1. An apparatus, comprising:

a package substrate having a first side opposing a second side, and comprising a first conductive layer on the first side of the package substrate, and a second conductive layer between the first side and the second side of the package substrate, the package substrate having a dielectric between the first conductive layer and the second conductive layer, wherein the first and second conductive layers comprise a plurality of pads and traces; and

at least one bridge die within the package substrate, the at least one bridge die having a first side opposing a second side, and comprising a plurality of vias extending from the first side to the second side of the at least one bridge die, wherein the at least one bridge die comprises a plurality of pads and traces on the first side of the at least one bridge die and a plurality of pads on the second side of the at least one bridge die, wherein the pads on the first side of the at least one bridge die are interconnected by the plurality of vias to the pads on the opposing second side of the at least one bridge die, and wherein the at least one bridge die comprises an adhesive conductive film on a bottom surface of a layer of silicon oxide on the second side of the at least one bridge die,

wherein a first active die and a second active die are coupled to the first side of the bridge die, wherein the second conductive layer between the first and second sides of the package substrate is coupled to the plurality of vias extending from the first side of the at least one bridge die to the second side of the at least one bridge die, wherein at least a portion of the plurality of vias extending between the first side and the second side of the at least one bridge die are coupled to power routing traces in the second conductive layer of the package substrate, and wherein the portion of the plurality of vias are to couple power from the package substrate to the first and second active dies.

2. The apparatus of claim 1, wherein at least a portion of the plurality of pads on the second side of the at least one bridge die are bonded to at least a portion of the plurality of pads of the second conductive layer of the package substrate.

3. The apparatus of claim 2, wherein solder joints are between the pads on the second side of the at least one bridge die bonded to the pads of the second conductive layer of the package substrate.

4. The apparatus of claim 1, wherein the dielectric is a first dielectric, and a second dielectric is between the second side of the at least one bridge die and the second conductive layer of the substrate.

5. The apparatus of claim 4, wherein the second dielectric is a die backside film.

6. The apparatus of claim 4, wherein the second dielectric is one of an epoxy flux film, an epoxy flux paste, or a wafer level underfill film.

7. The apparatus of claim 4, wherein the second dielectric surrounds solder joints between the plurality of pads on the second side of the at least one bridge die bonded to the plurality of pads in the second conductive layer of the package substrate.

8. The apparatus of claim 4, wherein the second dielectric is bonded to a portion of the first dielectric.

9. The apparatus of claim 1, wherein the adhesive conductive film is bonded to the first dielectric adjacent to the plurality of pads in the second conductive layer of the package substrate.

10. The apparatus of claim 1, wherein the first conductive layer of the package substrate is coupled to at least a portion of the plurality of pads and traces on the first side of the at least one bridge die.

11. The apparatus of claim 1, wherein the first active die comprises a first side opposed to a second side and a plurality of pads on the second side are bonded to the first side of the at least one bridge die.

12. The apparatus of claim 1, wherein a second plurality of vias extending between the first side and the second side of the at least one bridge die are coupled to signal routing traces in the second conductive layer of the package substrate.

13. The apparatus of claim 1, wherein the at least one bridge die comprises voltage regulation circuitry.

14. The apparatus of claim 13, wherein the voltage regulation circuitry comprises one or more fully integrated voltage regulator (FIVR) integrated circuits.

15. A system comprising:

a first active die having a first side opposing a second side, and comprising one or more logic integrated circuits formed on the first side and interconnected to a plurality of pads formed on the second side;

a second active die having a first side opposing a second side, and comprising one or more memory integrated circuits formed on the first side and interconnected to a plurality of pads formed on the second side; and

a package substrate comprising;

a first side opposing a second side, wherein a first conductive layer is on the first side of the package substrate, and a second conductive layer is between the first and second sides of the package substrate, and wherein the first and second conductive layers comprise a plurality of pads; and

traces wherein the package substrate comprises a dielectric between the first conductive layer and the second conductive layer; and

at least one bridge die within the package substrate and electrically coupled thereto, the at least one bridge die having a first side opposite a second side, the first side coupled to the first active die and the second active die, and comprising a plurality of vias extending from the first side to the second side of the at least one bridge die, wherein the at least one bridge die comprises a plurality of pads and traces on the first side of the at least one bridge die and a plurality of pads on the second side of the at least one bridge die, wherein the pads on the first side of the at least one bridge die are interconnected by the plurality of vias to the pads on the opposing second side of the at least one bridge die, and wherein the at least one bridge die comprises an adhesive conductive film on a bottom surface of a layer of silicon oxide on the second side of the at least one bridge die,

wherein the at least a portion of the plurality of vias extending between the first side and the second side of the at least one bridge die is coupled to power routing traces in the second conductor layer of the package substrate, wherein the portion of the plurality of vias are to couple power from the package substrate to the first and second active dies,

and wherein the at least one bridge die is to route high-speed signals between the first active die and the second active die.

16. The system of claim 15, wherein at least a portion of the plurality of pads on the second side of the first active die and at least a portion of the plurality of pads on the second side of the second active die are bonded to at least a portion of the plurality of pads on the first side of the at least one bridge die.