Package-embedded thin-film capacitors, package-integral magnetic inductors, and methods of assembling same

• US 10,373,951 B1
• Filed: 06/25/2018
• Issued: 08/06/2019
• Est. Priority Date: 06/25/2018
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Xu, Cheng, Jain, Rahul, Kim, Seo Young, Lee, Kyu Oh, Park, Ji Yong, Vadlamani, Sai, Zhao, Junnan
• Primary Examiner(s): Coleman, William
• Application Number:
  US16/017,247
• Time in Patent Office: 407 Days
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/09 of a plurality of bonding areas
• CPC Class Codes: H01L 27/0788 comprising combinations of diodes or capacitors or resistors
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

Claims

1. A semiconductor package substrate, comprising:

a first build-up film including a first lithograph surface;

a second and adjacent build-up film including a recess that abuts the first lithographic surface;

a thin-film capacitor, wherein the thin-film capacitor is seated on the first lithographic surface, and at least partially embedded in the second and adjacent build-up film; and

a magnetic inductor, wherein the magnetic inductor includes an inductor trace and a first magnetic-particle body within the recess, and a complementary magnetic-particle body that contacts the inductor trace, the first magnetic-particle body and the first build-up film.

2. The semiconductor package substrate of claim 1, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side further including:

a semiconductive device contacting the die side, wherein the semiconductive device is coupled to the embedded thin-film capacitor and to the integral magnetic inductor, wherein the semiconductive device forms a die shadow on the die side, and wherein the die shadow overlaps the embedded thin-film capacitor and the integral magnetic inductor.

3. The semiconductor package substrate of claim 1, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side further including:

a ball-pad array on the die side, where ball-pad pad array is exposed through a die-side solder resist semiconductive device contacting the die side, wherein the ball-pad array is coupled to the embedded thin-film capacitor and to the integral magnetic inductor, wherein the ball-pad array forms a die shadow on the die side, and wherein the die shadow overlaps the embedded thin-film capacitor and the integral magnetic inductor.

4. The semiconductor package substrate of claim 1, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, further including:

a capacitor via that communicates to the die side and that contacts the thin-film capacitor.

5. The semiconductor package substrate of claim 1, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, further including:

a first capacitor via that communicates to the die side and that contacts the thin-film capacitor; and

a subsequent capacitor via that communicates to the die side and that contacts the thin-film capacitor.

6. The semiconductor package substrate of claim 1, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, and wherein the thin-film capacitor is a first thin-film capacitor, further including:

a first capacitor via that communicates to the die side and the contacts the first thin-film capacitor; and

a subsequent thin-film capacitor, wherein the subsequent thin-film capacitor is seated on the first lithographic surface, and partially embedded in the second and adjacent build-up film.

7. The semiconductor package substrate of claim 1, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, and wherein the thin-film capacitor is a first thin-film capacitor, further including:

a first capacitor via that communicates to the die side and that contacts the first thin-film capacitor;

a subsequent thin-film capacitor, wherein the subsequent thin-film capacitor is seated on the first lithographic surface, and partially embedded in the second and adjacent build-up film; and

wherein one of the first and subsequent thin-film capacitors is adjacent the magnetic inductor.

8. The semiconductor package substrate of claim 1, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, and the magnetic inductor is a first magnetic inductor, further including:

a capacitor via that communicates to the die side and that contacts the thin-film capacitor;

a subsequent magnetic inductor, wherein the subsequent magnetic inductor is adjacent one of the thin-film capacitor and the first magnetic inductor, wherein the subsequent magnetic inductor includes a subsequent inductor trace and a subsequent first magnetic-particle body within the recess, and a subsequent complementary magnetic-particle body that contacts the subsequent inductor trace, the subsequent first magnetic-particle body and the first build-up film.

9. The semiconductor package substrate of claim 1, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, wherein the recess is a first recess, and wherein the magnetic inductor is a first magnetic inductor, further including:

a capacitor via that communicates to the die side and that contacts the thin-film capacitor;

a subsequent magnetic inductor, wherein the subsequent magnetic inductor is adjacent one of the thin-film capacitor and the first magnetic inductor, wherein the subsequent magnetic inductor includes two subsequent inductor traces and a subsequent first magnetic-particle body within a subsequent recess with the second and adjacent build-up film, and a subsequent complementary magnetic-particle body that contacts the two subsequent inductor traces, the subsequent first magnetic-particle body and the first build-up film.

10. The semiconductor package substrate of claim 1, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, wherein the inductor trace is a first inductor trace, further including:

a capacitor via that communicates to the die side and that contacts the thin-film capacitor;

wherein the first inductor trace is one of two inductor traces that are contacted by the first magnetic-particle body within the recess, and the subsequent complementary magnetic-particle body.

11. The semiconductor package substrate of claim 1, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, wherein the recess is a first recess, and wherein the magnetic inductor is a first magnetic inductor, further including:

a capacitor via that communicates to the die side and that contacts the thin-film capacitor;

a subsequent magnetic inductor, wherein the subsequent magnetic inductor is adjacent one of the thin-film capacitor and the first magnetic inductor, wherein the subsequent magnetic inductor includes a subsequent inductor trace and a subsequent first magnetic-particle body within a subsequent recess within the second and adjacent build-up film, and a subsequent complementary magnetic-particle body that contacts the subsequent inductor trace, the subsequent magnetic-particle body and the first build-up film.

12. The semiconductor package substrate of claim 1, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, further including:

a semiconductive device contacting the die side, wherein the semiconductive device is coupled to the embedded thin-film capacitor and to the integral magnetic inductor;

an electrical bump on the land side; and

a board contacting the electrical bump.

13. The semiconductor package substrate of claim 1, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, further including:

a package via that communicates from the die side, through the first build-up film, the second and adjacent build-up film, and the further communicates to the land side.

14. The semiconductor package substrate of claim 1, wherein the thin-film capacitor includes, beginning at first lithographic surface, a copper-containing layer, a nickel-containing layer, a barium titanate (BTO) containing layer and a copper-containing layer.

15. The semiconductor package substrate of claim 1, wherein the thin-film capacitor includes, beginning at first lithographic surface, a first metal-containing layer, a subsequent metal-containing layer different from the first metal-containing layer, a dielectric layer and a third metal-containing layer.

16. A process of forming a semiconductor package substrate, comprising:

seating a thin-film capacitor on a first build-up film;

locating an inductor trace and a first magnetic-particle paste in a recess in an adjacent build up film;

locating a subsequent complementary magnetic-particle paste adjacent the first magnetic particle paste, wherein the subsequent complementary magnetic-particle paste contacts the inductor trace;

forming a land side and a die side that are coupled to the first and second and adjacent build-up films; and

wherein the die side includes a die footprint that overlaps the thin-film capacitor and the magnetic inductor.

17. The process of claim 16, wherein the thin-film capacitor is a first thin-film capacitor, further including seating a subsequent thin-film capacitor on the first build-up film.

18. The process of claim 16, wherein the inductor trace is a first inductor trace, further including locating a subsequent inductor trace with the first magnetic-particle paste in the recess in the adjacent build up film;

locating the subsequent complementary magnetic-particle paste adjacent the first magnetic particle paste, wherein the subsequent complementary magnetic-particle paste contacts the first inductor trace and the subsequent inductor trace.

19. A computing system, comprising:

a first build-up film of a semiconductor package substrate, wherein the first build-up film includes a first lithograph surface, and wherein the semiconductor package substrate includes a die side and a land side;

a second and adjacent build-up film including a recess that abuts the first lithographic surface;

a thin-film capacitor, wherein the thin-film capacitor is seated on the first lithographic surface, and partially embedded in the second and adjacent build-up film;

a first capacitor via that communicates to the die side and that contacts the thin-film capacitor;

a subsequent capacitor via that communicates to the die side and that contacts the thin-film capacitor;

a subsequent thin-film capacitor, wherein the subsequent thin-film capacitor is seated on the first lithographic surface, and partially embedded in the second and adjacent build-up film;

a magnetic inductor, wherein the magnetic inductor includes an inductor trace and a first magnetic-particle body within the recess, and a complementary magnetic-particle body that contacts the inductor trace, the first magnetic-particle body and the first build-up film;

a semiconductive device contacting the die side, wherein the semiconductive device is coupled to the embedded thin-film capacitor and to the integral magnetic inductor, wherein the semiconductive device forms a die shadow on the die side, and wherein the die shadow overlaps the embedded thin-film capacitor and the integral magnetic inductor; and

a board contacting the semiconductor package substrate at the land side.

20. The computing system of claim 19, wherein the board is part of a data server.

21. The computing system of claim 19, wherein the board includes an external shell.

22. The computing system of claim 19, further wherein the semiconductive device is part of a chip set.

23. The computing system of claim 19 further wherein the semiconductive device is part of a chipset, wherein the board includes an external shell and wherein the embedded thin-film capacitor is one of more than three embedded thin-film capacitors.