Semiconductor memory device and method of fabricating the same

• US 10,373,959 B2
• Filed: 07/31/2018
• Issued: 08/06/2019
• Est. Priority Date: 09/18/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Im, Dong-Hyun, Kim, Daehyun, Park, Hoon, Seo, Jae-Hong, Chung, Chunhyung, Choi, Jae-Joong
• Primary Examiner(s): Fourson, III, George R
• Application Number:
  US16/050,848
• Publication Number:
  US 20190088657A1
• Time in Patent Office: 371 Days
• CPC Class Codes: H01L 21/28026 characterised by the conductor H01L21/28176 takes precedence
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

A method of fabricating a semiconductor memory device includes etching a substrate that forms a trench that crosses active regions of the substrate, forming a gate insulating layer on bottom and side surfaces of the trench, forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench, oxidizing a top surface of the first gate electrode where a preliminary barrier layer is formed, nitrifying the preliminary barrier layer where a barrier layer is formed, and forming a second gate electrode on the barrier layer that fills an upper portion of the trench.

Claims

1. A method of fabricating a semiconductor memory device, comprising:

etching a substrate wherein a trench is formed that crosses active regions of the substrate;

forming a gate insulating layer on bottom and side surfaces of the trench;

forming a first gate electrode on the gate insulating layer that fills a lower portion of the trench;

oxidizing a top surface of the first gate electrode wherein a preliminary barrier layer is formed;

nitrifying the preliminary barrier layer wherein a barrier layer is formed; and

forming a second gate electrode on the barrier layer that fills an upper portion of the trench.

2. The method of claim 1, wherein nitrifying the preliminary barrier layer nitrifies an exposed portion of the gate insulating layer located above the first gate electrode.

3. The method of claim 1, wherein nitrifying the preliminary barrier layer nitrifies an upper portion of the first gate electrode.

4. The method of claim 1, wherein

oxidizing the top surface of the first gate electrode injects oxygen atoms into the first gate electrode, and

nitrifying the preliminary barrier layer injects nitrogen atoms into crystalline defects of the preliminary barrier layer.

5. The method of claim 1, further comprising etching the gate insulating layer before forming the second gate electrode, wherein a thickness of a portion of the gate insulating layer exposed above the barrier layer is reduced.

6. The method of claim 1, wherein the first gate electrode comprises a first metal, and

the barrier layer comprises an oxynitride of the first metal.

7. The method of claim 1, further comprising forming a liner layer that covers a top surface of the barrier layer and a side surface of the gate insulating layer exposed above the barrier layer, before forming the second gate electrode.

8. The method of claim 1, further comprising forming a capping layer on the second gate electrode that fills a remaining region of the trench.

9. A semiconductor memory device, comprising:

a semiconductor substrate that includes a trench;

a gate insulating layer disposed in the trench that covers bottom and inner side surfaces of the trench;

a first gate electrode disposed in a lower portion of the trench, the first gate electrode including a first metal;

a second gate electrode disposed in the trench and on the first gate electrode; and

a barrier layer disposed between the first and second gate electrodes, the barrier layer including an oxynitride of the first metal,

wherein the second gate electrode has a work-function that is less than the work-function of the first gate electrode.

10. The device of claim 9, wherein the gate insulating layer has a first portion adjacent to the first gate electrode and a second portion adjacent to the second gate electrode, and

when measured in a direction perpendicular to a side surface of the trench, the first portion is thicker than the second portion.

11. The device of claim 10, wherein a thickness of the first portion is about 40% to 70% greater than a thickness of the second portion.

12. The device of claim 9, wherein the second gate electrode is wider than the first gate electrode.

13. The device of claim 9, wherein a nitrogen concentration of a portion of the gate insulating layer adjacent to the second gate electrode is greater than the nitrogen concentration of a portion of the gate insulating layer adjacent to the first gate electrode.

14. The device of claim 9, wherein a thickness of the barrier layer ranges from 1 Å

to 30 Å

.

15. The device of claim 9, wherein the second gate electrode comprises poly-silicon doped with n-type impurities.

16. The device of claim 9, wherein the first gate electrode and the second gate electrode are spaced apart from each other by the barrier layer.

17. The device of claim 9, further comprising a liner layer disposed between the barrier layer and the second gate electrode,

wherein the liner layer extends into a space between the gate insulating layer and the second gate electrode.

18. The device of claim 9, wherein the substrate further comprises:

active regions surrounded by a device isolation layer, wherein the active regions extend in a direction that crosses the trenches; and

doped regions formed in the active regions,

wherein the doped regions comprise first doped regions disposed between the trenches, and second doped regions disposed between the trenches and the device isolation layer.

19. The device of claim 18, further comprising

bit lines disposed on the substrate and connected to the first doped regions;

and

capacitors disposed on the substrate and connected to the second doped regions.

20. A semiconductor memory device, comprising:

a substrate that includes active regions surrounded by a device isolation layer, the active regions extending in a first direction;

gate lines buried in trenches formed in an upper portion of the substrate, wherein the gate lines cross the active regions in a second direction that crosses the first direction and divide the active regions into first and second doped regions; and

a bit line disposed on the gate lines that extends in a third direction that crosses both of the first and second directions,

wherein each of the gate lines comprises;

a first gate electrode disposed in a lower portion of the trench, wherein a top surface of the first gate electrode includes oxygen and nitrogen atoms; and

a second gate electrode disposed on the first gate electrode.