Semiconductor device

• US 10,373,976 B2
• Filed: 06/20/2014
• Issued: 08/06/2019
• Est. Priority Date: 07/05/2013
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Fukuzaki, Yuzo, Ammo, Hiroaki
• Primary Examiner(s): Bell, Lauren R
• Application Number:
  US14/310,689
• Publication Number:
  US 20150008525A1
• Time in Patent Office: 1,873 Days
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes: a substrate; an insulator layer provided on the substrate; a first transistor provided on the insulator layer; a semiconductor layer including a plurality of impurity regions of a first conduction type, the impurity regions forming a part of the first transistor; a heat dissipation layer; a thermal conductive layer linking the semiconductor layer and the heat dissipation layer; and an interruption structure configured to interrupt a flow of a current between the first transistor and the thermal conductive layer.

Claims

1. A semiconductor device comprising:

a bulk substrate having an upper surface;

an insulator layer directly on a portion but not all of the upper surface of the bulk substrate so as to leave a bulk region uncovered by the insulator layer, the bulk region being outside of a periphery of the insulator layer, the insulator layer having an element separation region received within a recess in the upper surface, the element separation region surrounding an element formation region of the semiconductor device and laterally separating and isolating the element formation region of the semiconductor device from the bulk region along the upper surface;

a semiconductor layer on the insulator layer and within the element formation region;

a first transistor on the semiconductor layer, the first transistor including a gate and first source and drain regions in the semiconductor layer, the first source and drain regions each being of a first conductivity type;

a thermally conductive path linking the semiconductor layer and the bulk region, the thermally conductive path including a thermally conductive layer; and

an interruption structure adjacent to and in series with the first transistor, not isolated from the first transistor along the semiconductor layer, and configured and connected to selectively interrupt a flow of a current between the first transistor and the thermally conductive path, the thermally conductive path bridging over the recess and overlapping the periphery of the insulator layer.

2. The semiconductor device according to claim 1, further comprising a second transistor on the semiconductor layer, wherein:

the second transistor is the interruption structure,

the second transistor includes a second gate and second source and drain regions in the semiconductor layer, the second source and drain regions each being of the first conductivity type, and

the thermally conductive layer links the second source region or second drain region of the second transistor with the bulk region.

3. The semiconductor device according to claim 1, comprising two second transistors, the first transistor being between the two second transistors in an in-plane direction, one of the two second transistors being the interruption structure.

4. The semiconductor device according to claim 1, comprising a plurality of the first transistors and two second transistors, wherein:

the plurality of the first transistors are arranged along a first direction,

the plurality of the first transistors are between the two second transistors along the first direction,

one of the two second transistors is the interruption structure.

5. The semiconductor device according to claim 4, wherein the thermally conductive layer is connected to a source electrode or a drain electrode of the one of the two second transistors.

6. The semiconductor device according to claim 5, wherein application of an electric potential to a gate of the one of the two second transistors causes the one of the two second transistors to be in an OFF state.

7. The semiconductor device according to claim 1, wherein:

the semiconductor layer includes an impurity region of a second conductivity type which is different than the first conductivity type, as the interruption structure, and

the thermally conductive layer links the impurity region of the second conduction type, with the bulk region.

8. The semiconductor device according to claim 7 comprising two of the impurity regions, wherein the first transistor is provided between the two impurity regions in an in-plane direction.

9. A semiconductor device comprising:

a bulk substrate having an upper surface;

an insulator layer directly on a portion but not all of the upper surface so as to leave a bulk region uncovered by the insulator layer, the bulk region being outside of a periphery of the insulator layer, the insulator layer having an element separation region received within a recess in the upper surface, the element separation region surrounding an element formation region of the semiconductor device laterally separating and isolating the element formation region of the semiconductor device from the bulk region along the upper surface;

a thin film semiconductor layer on the insulator layer and within the element formation region;

a first MOSFET on the thin film semiconductor layer with source/drain regions in the thin film semiconductor layer;

a second MOSFET on the thin film semiconductor with source/drain regions in the thin film semiconductor layer, the first and second MOSFETs sharing in common one of the source/drain regions; and

a thermally conductive path linking the thin film semiconductor layer and the bulk region, with the second MOSFET between the thermally conductive path and the first MOSFET, the thermally conductive path including a thermally conductive layer, the thermally conductive path bridging over the recess and overlapping the periphery of the insulator layer.

10. The semiconductor device of claim 9, wherein the first and second MOSFETs are finFETs.

11. The semiconductor device of claim 9, comprising a plurality of the first MOSFETs and two of the second MOSFETs, wherein the plurality of the first MOSFETs are arranged in series between the two second MOSFETs.