Undercut control in isotropic wet etch processes

• US 10,374,034 B1
• Filed: 05/21/2018
• Issued: 08/06/2019
• Est. Priority Date: 05/21/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Liu, Chi-Chun, Sankarapandian, Muthumanickam, Schmidt, Kristin, De Silva, Ekmini Anuja, Arellano, Noel, Chao, Robin Hsin Kuo, Yeung, Chun Wing, Bi, Zhenxing
• Primary Examiner(s): Nicely, Joseph C.
• Application Number:
  US15/985,189
• Time in Patent Office: 442 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02606 Nanotubes carbon nanotubes H10K85/211
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/321 After treatment
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0669 Nanowires or nanotubes carbon nanotubes as material of solid-state device active part H10K85/211
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method for manufacturing a semiconductor device includes forming a first nanosheet device and forming a second nanosheet device spaced apart from the first nanosheet device in respective first and second regions corresponding to first and second types. The first and second nanosheet devices respectively include a first and a second plurality of work function metal layers, and a work function metal layer extends from the first and second plurality of work function metal layers in the space between the nanosheet devices. In the method, part of the work function metal layer is removed from the space between the nanosheet devices, and the removed part of the work function metal layer is replaced with a polymer brush layer. The first plurality of work function metal layers is selectively removed from the first region with respect to the polymer brush layer.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a first nanosheet device in a first region corresponding to a first type, wherein the first nanosheet device comprises a first plurality of work function metal layers;

forming a second nanosheet device spaced apart from the first nanosheet device in a second region corresponding to a second type, wherein the second nanosheet device comprises a second plurality of work function metal layers, and wherein a work function metal layer extends from the first and second plurality of work function metal layers to a space between the first and second nanosheet devices;

forming an organic planarization layer in the second region covering the second nanosheet device and a first part of the work function metal layer in the space between the first and second nanosheet devices;

removing a second part of the work function metal layer not covered by the organic planarization layer from the space between the first and second nanosheet devices;

removing a portion of the first part of the work function metal layer under the organic planarization layer;

replacing removed areas of the work function metal layer with a polymer brush layer; and

selectively removing the first plurality of work function metal layers with respect to the polymer brush layer from the first region.

2. The method according to claim 1, further comprising:

forming a first spacer layer on the first plurality of work function metal layers; and

forming a second spacer layer on the organic planarization layer.

3. The method according to claim 2, wherein the first and second spacer layers comprise silicon oxide.

4. The method according to claim 2, wherein a portion of the second part of the work function metal layer is removed from under the second spacer layer.

5. The method according to claim 2, wherein a portion of the second part of the work function metal layer is removed from under the first spacer layer.

6. The method according to claim 2, further comprising selectively removing the first and second spacer layers with respect to the polymer brush layer.

7. The method according to claim 2, wherein a high-k dielectric layer is formed under the work function metal layer.

8. The method according to claim 7, wherein replacing the removed areas of the work function metal layer with the polymer brush layer comprises selectively forming the polymer brush layer on the high-k dielectric layer.

9. The method according to claim 7, wherein a material of the polymer brush layer grafts at a faster rate on the high-k dielectric layer than on the first and second spacer layers.

10. The method according to claim 7, wherein a material of the polymer brush layer grafts at a faster rate on the high-k dielectric layer than on the organic planarization layer.

11. The method according to claim 1, wherein replacing the removed areas of the work function metal layer with a polymer brush layer comprises performing an annealing process at a temperature in the range of about 120°

C. to about 140°

C.

12. The method according to claim 1, further comprising:

removing part of the first plurality of work function metal layers from an upper portion of the first nanosheet device;

replacing the removed part of the first plurality of work function metal layers with another polymer brush layer.

13. The method according to claim 1, further comprising removing the organic planarization layer and the polymer brush layer during the same removal process.

14. The method according to claim 1, wherein the polymer brush layer comprises at least one of polystyrene, polytetrafluoroethylene, polyimide and polypropylene.

15. A method for manufacturing a semiconductor device, comprising:

forming a first stacked transistor device in a first region corresponding to a first type, wherein the first stacked transistor device comprises a first plurality of work function metal layers;

forming a second stacked transistor device spaced apart from the first stacked transistor device in a second region corresponding to a second type, wherein the second stacked transistor device comprises a second plurality of work function metal layers, and wherein a work function metal layer extends from the first and second plurality of work function metal layers to a space between the first and second stacked transistor devices;

depositing a mask layer to cover the second stacked transistor device and portions adjacent the second stacked transistor device in the second region;

removing part of the work function metal layer from the space between the first and second stacked transistor devices;

replacing the removed part of the work function metal layer with a polymer brush layer; and

selectively removing the first plurality of work function metal layers with respect to the polymer brush layer from the first region.

16. A method for manufacturing a semiconductor device, comprising:

forming a first plurality of stacked channel portions in a first region corresponding to a first type, wherein the first plurality of stacked channel portions are alternatingly stacked with a first plurality of work function metal layers;

forming a second plurality of stacked channel portions spaced apart from the first plurality of stacked channel portions in a second region corresponding to a second type, wherein the second plurality of stacked channel portions are alternatingly stacked with a second plurality of work function metal layers, and a work function metal layer extends from the first and second plurality of work function metal layers to a space between the first and second plurality of stacked channel portions;

forming an organic planarization layer in the second region covering the second plurality of stacked channel portions and covering a first part of the work function metal layer in the space between the first and second plurality of stacked channel portions;

removing a second part of the work function metal layer not covered by the organic planarization layer from the space between the first and second plurality of stacked channel portions;

removing a portion of the first part of the work function metal layer under the organic planarization layer;

replacing removed areas of the work function metal layer with a polymer brush layer; and

selectively removing the first plurality of work function metal layers with respect to the polymer brush layer from the first region.

17. The method according to claim 16, further comprising:

forming a first spacer layer on the first plurality of work function metal layers; and

forming a second spacer layer on the organic planarization layer.

18. The method according to claim 17, wherein a portion of the second part of the work function metal layer is removed from under the second spacer layer.

19. The method according to claim 17, wherein a high-k dielectric layer is formed under the work function metal layer.

20. The method according to claim 19, wherein replacing the removed areas of the work function metal layer with the polymer brush layer comprises selectively forming the polymer brush layer on the high-k dielectric layer.