Semiconductor devices and a method for forming a semiconductor device

• US 10,374,078 B2
• Filed: 03/10/2017
• Issued: 08/06/2019
• Est. Priority Date: 03/11/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Blank, Oliver, Wutte, Britta
• Primary Examiner(s): Chang, Jay C
• Assistant Examiner(s): Liu, Mikka
• Application Number:
  US15/455,965
• Publication Number:
  US 20170263756A1
• Time in Patent Office: 879 Days
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a plurality of striped-shaped trenches extending into a semiconductor substrate. At least one trench of a first group of trenches of the plurality of striped-shaped trenches is located between two trenches of a second group of trenches of the plurality of striped-shaped trenches. A gate of a transistor structure is located in each trench of the second group of trenches and a gate insulation layer is located between the gate and the semiconductor substrate in each trench of the second group of trenches. Trench insulation material is located in each trench of the first group of trenches. A thickness of the trench insulation material throughout each trench of the first group of trenches is at least two times larger than a thickness of the gate insulation layer in each trench of the second group of trenches.

Claims

1. A semiconductor device, comprising:

a plurality of striped-shaped trenches extending into a semiconductor substrate,

wherein at least one trench of a first group of trenches of the plurality of striped-shaped trenches is located between two trenches of a second group of trenches of the plurality of striped-shaped trenches,

wherein a gate of a transistor structure is located in each trench of the second group of trenches and a gate insulation layer is located between the gate and the semiconductor substrate in each trench of the second group of trenches,

wherein a trench insulation material is located in each trench of the first group of trenches,

wherein a thickness of the trench insulation material throughout each trench of the first group of trenches is at least two times larger than a thickness of the gate insulation layer in each trench of the second group of trenches,

wherein each trench of the first group of trenches comprises an electrode-free region,

wherein the electrode-free region occupies an equivalent location and volume in each trench of the first group of trenches as occupied by the gate in each trench of the second group of trenches,

wherein at least part of a field electrode located in each trench of the first group of trenches is located below a vertical level of the gates located in the trenches of the second group of trenches.

2. The semiconductor device of claim 1, wherein an average depth of the trenches of the first group of trenches is equal to an average depth of the trenches of the second group of trenches.

3. The semiconductor device of claim 1, wherein at least part of each electrode-free region is located in each trench of the first group of trenches at the same vertical level as the gate in each trench of the second group of trenches.

4. The semiconductor device of claim 1, wherein at least part of each electrode-free region is located in each trench of the first group of trenches along the same lateral direction as the gate in each trench of the second group of trenches.

5. The semiconductor device of claim 1, wherein each electrode-free region of the trenches of the first group of trenches is filled with the trench insulation material.

6. The semiconductor device of claim 1, wherein each trench of the first group of trenches is gate-free.

7. The semiconductor device of claim 1, wherein the field electrodes located in the trenches of the first group of trenches are the only electrodes located in the trenches of the first group of trenches.

8. The semiconductor device of claim 1, further comprising a source electrode structure electrically connected to the field electrodes located in the trenches of the first group of trenches.

9. The semiconductor device of claim 1, wherein a field electrode located in each trench of the second group of trenches is located laterally between a first gate of a first transistor structure and a second gate of a second transistor structure located in each trench of the second group of trenches.

10. The semiconductor device of claim 1, wherein n trenches of the first group of trenches and m trenches of the second group of trenches are arranged alternatingly in a lateral direction along the semiconductor substrate, wherein n and m are integers greater than or equal to 1.

11. The semiconductor device of claim 1, wherein a blocking voltage of the semiconductor device is greater than 10 V.

12. The semiconductor device of claim 1, wherein the first group of trenches and the second group of trenches have identical geometries.

13. A semiconductor device, comprising:

a plurality of striped-shaped trenches extending into a semiconductor substrate,

wherein at least one trench of a first group of trenches of the plurality of striped-shaped trenches is located between two trenches of a second group of trenches of the plurality of striped-shaped trenches,

wherein a gate of a transistor structure is located in each trench of the second group of trenches and a gate insulation layer is located between the gate and the semiconductor substrate in each trench of the second group of trenches,

wherein a trench insulation material is located in each trench of the first group of trenches,

wherein a thickness of the trench insulation material throughout each trench of the first group of trenches is at least two times larger than a thickness of the gate insulation layer in each trench of the second group of trenches,

wherein a field electrode located in each trench of the second group of trenches is located laterally between a first gate of a first transistor structure and a second gate of a second transistor structure located in each trench of the second group of trenches.

14. A semiconductor device, comprising:

a plurality of striped-shaped trenches extending into a semiconductor substrate,

wherein at least one trench of a first group of trenches of the plurality of striped-shaped trenches is located between two trenches of a second group of trenches of the plurality of striped-shaped trenches,

wherein a gate of a transistor structure is located in each trench of the second group of trenches and a gate insulation layer is located between the gate and the semiconductor substrate in each trench of the second group of trenches,

wherein a trench insulation material is located in each trench of the first group of trenches,

wherein a thickness of the trench insulation material throughout each trench of the first group of trenches is at least two times larger than a thickness of the gate insulation layer in each trench of the second group of trenches,

wherein each trench of the first group of trenches comprises an electrode-free region,

wherein the electrode-free region occupies an equivalent location and volume in each trench of the first group of trenches as occupied by the gate in each trench of the second group of trenches,

wherein a field electrode located in each trench of the second group of trenches is located laterally between a first gate of a first transistor structure and a second gate of a second transistor structure located in each trench of the second group of trenches.