Dynamic hysteresis circuit

• US 10,374,583 B1
• Filed: 04/02/2018
• Issued: 08/06/2019
• Est. Priority Date: 04/02/2018
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Olejarz, Piotr, Saari, Daniel, Arakelian, Ara
• Primary Examiner(s): Chen, Sibin
• Application Number:
  US15/943,341
• Time in Patent Office: 491 Days
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation
• CPC Class Codes: G06F 16/60 of audio data
• CPC Class Codes: H03K 3/02337 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165
• CPC Class Codes: H03K 3/0377 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165
• CPC Class Codes: H03K 5/086 generated by feedback
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H04J 3/0638 Clock or time synchronisation among nodes; Internode synchronisation synchronization for ring networks H04L12/422; data switching networks with synchronous transmission H04L12/43
• CPC Class Codes: H04J 3/0647 Synchronisation among TDM nodes
• CPC Class Codes: H04J 3/0652 Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP] bus network with centralized control in which slots are of a TDMA packet structure H04L12/4035
• CPC Class Codes: H04L 12/40006 Architecture of a communication node current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A method is described and in one embodiment includes detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode; placing the circuit in a second hysteresis mode subsequent to the detecting; and returning the receiver to the first hysteresis mode subsequent to completion of receipt of the data packet to await receipt of a next data packet. In certain embodiments, the first hysteresis mode is a high hysteresis mode and the second hysteresis mode is a standard hysteresis mode. In some embodiments, a level of each of the first and second hysteresis modes is dynamically tunable.

Claims

1. A method comprising:

detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode;

placing the circuit in a second hysteresis mode subsequent to the detecting; and

returning the circuit to the first hysteresis mode subsequent to completion of receipt of the data packet to await receipt of a next data packet;

wherein the circuit comprises a comparator and wherein the returning the circuit to the first hysteresis mode comprises dynamically decreasing a number of devices comprising a feedback circuit of the comparator.

2. The method of claim 1, wherein the first hysteresis mode is a high hysteresis mode and the second hysteresis mode is a standard hysteresis mode.

3. The method of claim 1, wherein a level of each of the first and second hysteresis modes is dynamically tunable.

4. The method of claim 1, wherein the completion of receipt of the data packet is indicated by deactivation of a receiver enable signal.

5. The method of claim 1, wherein the transition comprises a LOW to HIGH transition of the data signal.

6. The method of claim 1, wherein the transition comprises a HIGH to LOW transition of the data signal.

7. The method of claim 1, wherein the transition comprises a first edge of the data packet.

8. The method of claim 1, wherein the transition comprises an Nth transition of the data signal.

9. The method of claim 1, wherein circuit comprises a comparator and wherein the placing the circuit in the second hysteresis mode comprises dynamically increasing a number of devices comprising a feedback circuit of the comparator.

10. An apparatus comprising:

first circuitry for detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode;

second circuitry for placing the circuit in a second hysteresis mode subsequent to the detecting; and

third circuitry for returning the circuit to the first hysteresis mode subsequent to completion of receipt of the data packet to await a next data packet;

wherein the circuit comprises a comparator and wherein the placing the circuit in the second hysteresis mode comprises dynamically increasing a number of devices comprising a feedback circuit of the comparator.

11. The apparatus of claim 10, wherein the first hysteresis mode is a high hysteresis mode and the second hysteresis mode is a standard hysteresis mode and wherein a level of each of the first and second hysteresis modes is dynamically tunable.

12. The apparatus of claim 10, wherein the transition comprises one of a LOW to HIGH transition and a HIGH to LOW transition.

13. The apparatus of claim 10, wherein the transition comprises a first edge of the data packet.

14. The apparatus of claim 10, wherein the transition comprises an Nth transition of the data signal.

15. The apparatus of claim 10, wherein the circuit comprises a comparator and wherein the returning the circuit to the first hysteresis mode comprises dynamically decreasing a number of devices comprising a feedback circuit of the comparator.

16. The apparatus of claim 10 wherein the comparator comprises:

a comparator core; and

a plurality of pairs of cross-coupled devices, wherein a number of the cross-coupled devices connected to provide a feedback circuit for the comparator core is dynamically controllable to control a hysteresis level of the comparator.

17. The apparatus of claim 16, wherein the number of the cross-coupled devices connected to provide a feedback circuit for the comparator core is dynamically controllable via a control current.

18. A method comprising:

detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode;

placing the circuit in a second hysteresis mode subsequent to the detecting; and

returning the circuit to the first hysteresis mode subsequent to completion of receipt of the data packet to await receipt of a next data packet;

wherein circuit comprises a comparator and wherein the placing the circuit in the second hysteresis mode comprises dynamically increasing a number of devices comprising a feedback circuit of the comparator.

19. The method of claim 18, wherein a level of each of the first and second hysteresis modes is dynamically tunable.

20. The method of claim 18, wherein the transition comprises an Nth transition of the data signal.