Injection-locked digital bang-bang phase-locked loop with timing calibration
First Claim
1. A phase-locked loop (PLL) circuit comprising:
- a phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection;
a down-sampling circuit connected to the input clock signal connection;
a digitally-controlled delay line receiving an output of the down-sampling circuit;
an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to a portion of the phase-locked loop (PLL); and
an injection timing calibration circuit connected to a control input of the digitally-controlled delay line.
1 Assignment
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Accused Products
Abstract
A phase-locked loop circuit is disclosed. The circuit includes a digital bang-bang phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection, and a down-sampling circuit connected to the input clock signal connection. The circuit also includes a digitally-controlled delay line receiving an output of the down-sampling circuit, and an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to a portion of the digital bang-bang phase-locked loop (PLL). The circuit further includes an injection timing calibration circuit connected to a control input of the digitally-controlled delay line. The circuit provides calibration of injection timing and bandwidth optimization, thereby reducing jitter in an output signal from the PLL.
5 Citations
20 Claims
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1. A phase-locked loop (PLL) circuit comprising:
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a phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection; a down-sampling circuit connected to the input clock signal connection; a digitally-controlled delay line receiving an output of the down-sampling circuit; an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to a portion of the phase-locked loop (PLL); and an injection timing calibration circuit connected to a control input of the digitally-controlled delay line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of reducing jitter in a phase-locked loop, the method comprising:
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receiving a clock signal at a phase-locked loop and a down-sampling circuit; based on a sign of the clock signal captured by a phase frequency detector included in the phase-locked loop, calibrating an injection signal timing and enabling output of the down-sampling circuit; providing an injection signal to a digitally-controlled oscillator included in the phase-locked loop based at least in part on output of an injection pulser receiving an output of a digitally-controlled delay line, the digitally controlled delay line controlled by the calibrated injection signal timing to apply a variable delay to an output from the down-sampling circuit; and outputting a clock signal from the digitally-controlled oscillator based at least in part on the output signal received from the injection pulser. - View Dependent Claims (10, 11, 12)
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13. An injection-locked digital bang-bang phase-locked loop (PLL) circuit comprising:
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a digital bang-bang phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection, the digital bang-bang PLL comprising; a bang-bang phase frequency detector; a digital loop filter connected to a signal output of the bang-bang phase frequency detector; a digitally controlled oscillator receiving an output signal of the digital loop filter, the digitally controlled oscillator configured to output a resulting clock signal at the output clock signal connection; and a divider providing a signal feedback from an output of the digitally controlled oscillator to the bang-bang phase frequency detector; a down-sampling circuit connected to the input clock signal connection; a digitally-controlled delay line receiving an output of the down-sampling circuit; an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to the digitally controlled oscillator; an injection timing calibration circuit connected to a control input of the digitally-controlled delay line; and a bandwidth optimization circuit connected to the signal output of the bang-bang phase frequency detector and having a control output connected to the digital loop filter. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification