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Frequency locked loop with multi-bit sampler

  • US 10,374,618 B1
  • Filed: 07/26/2018
  • Issued: 08/06/2019
  • Est. Priority Date: 03/29/2018
  • Status: Active Grant
First Claim
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1. A frequency locked loop (FLL) comprising:

  • a frequency detection unit, which is configured to receive a reference frequency parameter and a sub-sampled frequency parameter, and to generate a digital frequency difference, wherein the digital frequency difference is a difference indication between the reference frequency parameter and the sub-sampled frequency parameter;

    a local oscillator (LO) configured to generate an output signal based on the digital frequency difference; and

    a multi-bit sampler configured to update the sub-sampled frequency parameter applied to the frequency detection unit by sub-sampling the output signal with N sampling-clocks, wherein;

    N is greater than or equal to 2;

    the N sampling-clocks have a same sampling frequency and are sequentially offset by an equal time delay between adjacent sampling-clocks; and

    the updated sub-sampled frequency parameter monotonically maps an output frequency of the output signal.

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