Frequency locked loop with multi-bit sampler

• US 10,374,618 B1
• Filed: 07/26/2018
• Issued: 08/06/2019
• Est. Priority Date: 03/29/2018
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Roodnat, Anton Willem, Van Driest, Hans
• Primary Examiner(s): Cox, Cassandra F
• Application Number:
  US16/046,513
• Time in Patent Office: 376 Days
• Field of Search: None
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/189 comprising a D/A converter for generating a coarse tuning voltage

Abstract

The present disclosure relates to a frequency locked loop including a frequency detection unit, a local oscillator, and a multi-bit sampler. The frequency detection unit is configured to receive a reference frequency parameter and a sub-sampled frequency parameter, and configured to generate a digital frequency difference, which is a difference indication between the reference frequency parameter and the sub-sampled frequency parameter. The local oscillator is configured to generate an output signal based on the digital frequency difference. The multi-bit sampler is configured to update the sub-sampled frequency parameter by sub-sampling the output signal with N (N>=2) sampling-clocks. The N sampling-clocks have a same sampling frequency and are sequentially offset by an equal time delay between adjacent sampling-clocks. The updated sub-sampled frequency parameter monotonically maps an output frequency of the output signal.

Claims

1. A frequency locked loop (FLL) comprising:

a frequency detection unit, which is configured to receive a reference frequency parameter and a sub-sampled frequency parameter, and to generate a digital frequency difference, wherein the digital frequency difference is a difference indication between the reference frequency parameter and the sub-sampled frequency parameter;

a local oscillator (LO) configured to generate an output signal based on the digital frequency difference; and

a multi-bit sampler configured to update the sub-sampled frequency parameter applied to the frequency detection unit by sub-sampling the output signal with N sampling-clocks, wherein;

N is greater than or equal to 2;

the N sampling-clocks have a same sampling frequency and are sequentially offset by an equal time delay between adjacent sampling-clocks; and

the updated sub-sampled frequency parameter monotonically maps an output frequency of the output signal.

2. The FLL of claim 1 wherein the multi-bit sampler comprises N sub-sampling units, wherein each of the N sub-sampling units is clocked by a corresponding one of the N sampling-clocks and configured to provide a sub-sampling output based on the output signal from the LO.

3. The FLL of claim 2 wherein each of the N sub-sampling units is a one-bit unit and the sub-sampling output is a one-bit signal.

4. The FLL of claim 2 wherein the multi-bit sampler further comprises a phase coder and a phase to frequency converter, wherein:

the phase coder is configured to receive the sub-sampling output from each of the N sub-sampling units and provide a phase word, which represents an initial phase state of the output signal; and

the phase to frequency converter is configured to receive the phase word and provide the sub-sampled frequency parameter.

5. The FLL of claim 4 wherein a transfer function of the phase to frequency converter is achieved by differentiation of the phase-word combined with a modulo operation.

6. The FLL of claim 2 wherein the output signal has a period T_OUT, and the time delay between the adjacent sampling-clocks equals to T_OUT/N.

7. The FLL of claim 6 wherein a phase-resolution of the multi-bit sampler is 360/N.

8. The FLL of claim 6 wherein the phase-word has a number of bits equal to log₂N.

9. The FLL of claim 2 wherein:

a duty cycle of the output signal is about 50%; and

the output signal has a period T_OUT and the time delay between the adjacent sampling-clocks is equal to T_OUT/2N.

10. The FLL of claim 9 wherein a phase-resolution of the multi-bit sampler is 180/N.

11. The FLL of claim 9 wherein the phase-word has a number of bits equal to log₂N+1.

12. The FLL of claim 9 wherein a transfer function of the phase to frequency converter is implemented as H(z)=mod (1−

z<sup>−

1</sup>, 2N).

13. The FLL of claim 1 wherein the LO is a voltage controlled oscillator.

14. The FLL of claim 13 further comprising:

a digital-to-analog converter (DAC) configured to provide an analog parameter based on the digital frequency difference; and

a loop filter configured to receive the analog parameter, smooth the analog parameter, and provide a voltage control signal to the LO, wherein the LO is configured to generate the output signal based on the voltage control signal.

15. The FLL of claim 14 further comprising a digital filter between the frequency detection unit and the DAC, wherein the digital filter is configured to attenuate frequency noise associated with the digital frequency difference and provide a filtered digital frequency difference to the DAC.

16. The FLL of claim 14 wherein the digital-to-analog converter is a delta-sigma modulator.

17. The FLL of claim 16 wherein the DAC includes a charge pump, such that the analog parameter provided by the DAC is current.

18. The FLL of claim 1 wherein the LO is a digitally controlled oscillator (DCO).

19. The FLL of claim 18 further comprising a loop filter between the frequency detection unit and the LO, wherein the loop filter is configured to receive the digital frequency difference and provide a digital control signal to the LO.

20. The FLL of claim 1 wherein the sampling frequency of the N sampling-clocks is at least 10 times slower than the output frequency of the output signal.