Systems, methods and apparatuses for secure time management

• US 10,374,811 B2
• Filed: 05/15/2017
• Issued: 08/06/2019
• Est. Priority Date: 06/18/2012
• Status: Active Grant

• Current Assignee: OLogN Technologies AG
• Original Assignee: OLogN Technologies AG
• Inventors: Ignatchenko, Sergey, Ivanchykhin, Dmytro
• Primary Examiner(s): Jhaveri, Jayesh M
• Application Number:
  US15/595,036
• Publication Number:
  US 20170317838A1
• Time in Patent Office: 813 Days
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/14 Time supervision arrangements, e.g. real time clock
• CPC Class Codes: G06F 12/1408 by using cryptography for digital transmission H04L9/00
• CPC Class Codes: G06F 21/725 operating on a secure reference time value
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: H04L 9/32 including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
• CPC Class Codes: H04L 9/3247 involving digital signatures
• CPC Class Codes: H04L 9/3263 involving certificates, e.g. public key certificate [PKC] or attribute certificate [AC]; Public key infrastructure [PKI] arrangements network architectures or network communication protocols for supporting authentication of entities using certificates in a packet data network H04L63/0823
• CPC Class Codes: H04L 9/3268 using certificate validation, registration, distribution or revocation, e.g. certificate revocation list [CRL]
• CPC Class Codes: H04L 9/3297 involving time stamps, e.g. generation of time stamps
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The systems, methods and apparatuses described herein provide a computing environment that includes secure time management. An apparatus according to the present disclosure may comprise a non-volatile storage to store a synchronization time and a processor. The processor may be configured to generate a request for a current time, transmit the request to a trusted timekeeper, receive a digitally signed response containing a current, real-world time from the trusted timekeeper, verify the digital signature of the response, verify that the response is received within a predefined time, compare a nonce in the request to a nonce in the response, determine that the current, real-world time received from the trusted timekeeper is within a range of a current time calculated at the apparatus and update the synchronization time with the current, real-world time in the response.

Claims

1. A computing system comprising:

a first counter configured to operate at a first frequency and increment a first count value, wherein the first counter operates in a first energy mode;

a second counter configured to operate at a second frequency and increment a second count value, wherein the second counter is configured to operate in a second energy mode and wherein the second frequency is different than the first frequency;

a non-volatile machine-readable memory configured to store one or more event data; and

a processor configured to;

determine a first current time value based upon at least one of the one or more event data comprising switching of energy modes between the first energy mode and the second energy mode in the computing system and at least one of the first count value and the second count value selected based on the switching; and

synchronize the first current time value with a second current time value upon determining that the second current time value is within a predetermined range of the first current time value.

2. The system of claim 1, wherein the computing system switches from operating in the first energy mode to operating in the second energy mode upon the processor identifying a lack of power supply for operating in the first energy mode.

3. The system of claim 1, further comprising a battery from which the computing system consumes energy operating in a second energy mode.

4. The system of claim 1, wherein the second energy mode is a low energy mode, and wherein the computing system consumes comparatively less energy operating in the second energy mode than operating in the first energy mode.

5. The system of claim 1, wherein the second frequency is comparatively lower than the first frequency, and wherein the computing system consumes comparatively less energy operating at the second frequency than operating at the first frequency.

6. The system of claim 1, wherein the first counter is configured to indicate a first elapsed time beginning at an initialization time of the computing system, wherein the first count value is based on the first elapsed time.

7. The system of claim 6, wherein the processor is further configured to update the event data to indicate the computing system is operating in the second energy mode, and

wherein the second counter is configured to indicate a second elapsed time representing an amount of time that the computing system operates in the second energy mode, wherein the second count value is based on the second elapsed time.

8. The system of claim 7, wherein the processor is further configured to:

switch the computing system from operating in the second energy mode to operating in the first energy mode; and

store into the non-volatile memory the second elapsed time representing the amount of time that the computing system operated in the second energy mode.

9. The system of claim 8, wherein the processor is further configured to determine an amount of timer drift for the second counter accumulated from the initialization time of the second counter based on the first elapsed time and a maximum drift time stored in the non-volatile memory.

10. The system of claim 9, wherein the processor is further configured to store into the non-volatile memory a value of the second counter at each instance the computing system switches operation between the first energy mode and the second energy mode, and

wherein the processor determines the amount of timer drift based on each value of the second counter at each instance the computing system switches operation between the first energy mode and the second energy mode.

11. A computer-implemented method for keeping time for a computing system, the method comprising:

incrementing, by a first counter of an apparatus operating at a first frequency, a first count value, wherein the first counter operates in a first energy mode;

incrementing, by a second counter of the apparatus operating at a second frequency, a second count value, wherein the second frequency is different than the first frequency and wherein the second counter is configured to operate in a second energy mode;

storing, by a non-volatile machine readable memory, one or more event data;

determining, by a processor of the apparatus, a first current time value based upon at least one of the one or more event data comprising switching of energy modes between the first energy mode and the second energy mode in the computing system and at least one of the first count value and the second count value selected based on the switching; and

synchronizing the first current time value with a second current time value upon the processor determining that the second current time value is within a predetermined range of the first current time value.

12. The method of claim 11, further comprising:

identifying, by the processor, a lack of power supply for operating in the first energy mode, and

switching from operating in the first energy mode to operating in the second energy mode.

13. The method of claim 11, wherein the computing system further comprises a battery from which the computing system consumes energy operating in a second energy mode.

14. The method of claim 12, wherein the second energy mode is a low energy mode, and wherein the computing system consumes comparatively less energy operating in the second energy mode than operating in the first energy mode.

15. The method of claim 12, wherein the second frequency is comparatively lower than the first frequency, and wherein the computing system consumes comparatively less energy operating at the second frequency than operating at the first frequency.

16. The method of claim 12, wherein the first counter is configured to indicate a first elapsed time beginning at an initialization time of the computing system, and wherein the first count value is based on the first elapsed time.

17. The method of claim 16, further comprising updating, by the processor, the event data in non-volatile memory to indicate that the computing system is operating in the second energy mode,

wherein the second counter is configured to indicate a second elapsed time representing an amount of time that the computing system operates in the second energy mode, wherein the second count value is based on the second elapsed time.

18. The method of claim 17, further comprising:

switching from operating in the second energy mode to operating in the first energy mode; and

storing, by the processor, into the non-volatile memory the second elapsed time representing the amount of time that the computing system operated in the second energy mode.

19. The method of claim 18, further comprising determining, by the processor, an amount of timer drift for the second counter accumulated from the initialization time of the second counter based on the first elapsed time and a maximum drift time stored in the non-volatile memory.

20. The method of claim 19, further comprising:

storing, by the processor, into the non-volatile memory a value of the second counter at each instance the computing system switches operation between the first energy mode and the second energy mode; and

determining, by the processor, the amount of timer drift based on each value of the second counter at each instance the computing system switches operation between the first energy mode and the second energy mode.