Clock-embedded vector signaling codes

• US 10,374,846 B2
• Filed: 07/10/2018
• Issued: 08/06/2019
• Est. Priority Date: 02/28/2014
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin, Holden, Brian, Simpson, Richard
• Primary Examiner(s): Ha, Dac V
• Application Number:
  US16/031,875
• Publication Number:
  US 20180324008A1
• Time in Patent Office: 392 Days
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828

Abstract

Vector signaling codes providing guaranteed numbers of transitions per unit transmission interval are described, along with methods and systems for their generation and use. The described architecture may include multiple communications sub-systems, each having its own communications wire group or sub-channel, clock-embedded signaling code, pre- and post-processing stages to guarantee the desired code transition density, and global encoding and decoding stages to first distribute data elements among the sub-systems, and then to reconstitute the received data from its received sub-system elements.

Claims

1. An apparatus comprising:

a global transmission encoder configured to accept input data and responsively generate a set of reduced-modulus data;

a data history pre-coder configured to accept the set of reduced-modulus data from the global transmission encoder and to produce a set of transmit data based on a modulo addition of the set of reduced-modulus data with a codeword index associated with a codeword transmitted in a preceding unit interval such that the set of transmit data is different than the codeword index;

a data encoder configured to encode the transmit data into symbols of a codeword of an orthogonal differential vector signaling (ODVS) code; and

,

a driver configured to transmit the symbols of the codeword via respective wires of a multi-wire bus.

2. The apparatus of claim 1, wherein the data history pre-coder comprises a storage element configured to store the codeword index associated with the codeword transmitted in the preceding unit interval.

3. The apparatus of claim 2, wherein the storage element comprises a flip-flop.

4. The apparatus of claim 1, wherein the ODVS code is selected from the group consisting of:

Ensemble Non-Return to Zero (ENRZ), S3, OCT, C18, S4, and P3.

5. The apparatus of claim 4, wherein the multi-wire bus comprises a plurality of channels carrying symbols of respective codewords of respective ODVS codes.

6. The apparatus of claim 5, wherein at least two channels of the multi-wire bus carry different ODVS codes.

7. The apparatus of claim 1, wherein the ODVS code comprises a set of M codewords, and wherein the set of reduced-modulus data has a modulus of M−

1.

8. The apparatus of claim 7, wherein the modulo addition has a modulus of M.

9. The apparatus of claim 1, further comprising a receiver comprising:

a receive circuit configured to receive a set of signals via the multi-wire bus, the received set of signals corresponding to symbols of a received codeword of the ODVS code;

a data decoder configured to generate a set of decoded signals by decoding the received set of signals;

a data post-decoder configured to accept the set of decoded signals and to produce received data based on the set of decoded signals and a set of decoded signals decoded in a preceding unit interval; and

,

a global decoder configured to accept the received data to be reconstituted into a received version of a second set of input data.

10. The apparatus of claim 9, wherein the receiver further comprises a clock extraction circuit configured to derive a clock signal from a transition in the received set of signals with respect to a previously received set of signals received in the preceding unit interval.

11. A method comprising:

receiving a set of input data and responsively generating a set of reduced-modulus data;

generating a set of transmit data based on a modulo addition of the set of reduced-modulus data with a codeword index associated with a codeword transmitted in a preceding unit interval such that the set of transmit data is different than the codeword index;

encoding the transmit data into symbols of a codeword of an orthogonal differential vector signaling (ODVS) code; and

,

transmitting the symbols of the codeword via respective wires of a multi-wire bus.

12. The method of claim 11, wherein the codeword index is stored in a storage element.

13. The method of claim 12, further comprising storing the transmit data in the storage element as a codeword index for generating transmit data in a subsequent unit interval.

14. The method of claim 11, wherein the ODVS code is selected from the group consisting of:

Ensemble Non-Return to Zero (ENRZ), S3, OCT, C18, S4, and P3.

15. The method of claim 14, wherein the multi-wire bus comprises a plurality of channels carrying symbols of respective codewords of respective ODVS codes.

16. The method of claim 15, wherein at least two channels of the multi-wire bus carry different ODVS codes.

17. The method of claim 11, wherein the ODVS code comprises a set of M codewords, and wherein the set of reduced-modulus data has a modulus of M−

1.

18. The method of claim 17, wherein the modulo addition has a modulus of M.

19. The method of claim 11, further comprising a receiver subsystem comprising:

receive a set of signals via the multi-wire bus, the received set of signals corresponding to symbols of a received codeword of the ODVS code;

generating a set of decoded signals by decoding the received set of signals;

generating received data based on the set of decoded signals and a set of decoded signals decoded in a preceding unit interval; and

,

reconstituting the received data into a received version of a second set of input data.

20. The method of claim 19, further comprising deriving a clock signal from a transition in the received set of signals.