Circuit boards and electronic packages with embedded tamper-respondent sensor

• US 10,378,925 B2
• Filed: 10/17/2018
• Issued: 08/13/2019
• Est. Priority Date: 09/25/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Brodsky, William L., Dragone, Silvio, Krabbenhoft, Roger S., Long, David C., Oggioni, Stefano S., Peets, Michael T., Santiago-Fernandez, William
• Primary Examiner(s): Phan, Minh Q
• Application Number:
  US16/162,679
• Publication Number:
  US 20190049269A1
• Time in Patent Office: 300 Days
• CPC Class Codes: G01D 5/16 by varying resistance
• CPC Class Codes: H05K 1/0275 Security details, e.g. tampering prevention or detection
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/182 associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
• CPC Class Codes: H05K 2201/09263 Meander
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2201/10151 Sensor
• CPC Class Codes: H05K 2201/10371 Shields or metal cases
• CPC Class Codes: H05K 3/30 Assembling printed circuits with electric components, e.g. with resistor
• CPC Class Codes: H05K 3/32 electrically connecting electric components or wires to printed circuits

Abstract

Electronic circuits, electronic packages, and methods of fabrication are provided. The electronic circuit includes a multilayer circuit board, and a tamper-respondent sensor embedded within the circuit board. The tamper-respondent sensor defines, at least in part, a secure volume associated with the multilayer circuit board. In certain implementations, the tamper-respondent sensor includes multiple tamper-respondent layers embedded within the circuit board including, for instance, one or more tamper-respondent frames and one or more tamper-respondent mat layers, with the tamper-respondent frame(s) being disposed, at least in part, above the tamper-respondent mat layer(s), which together define the secure volume where extending into the multilayer circuit board. In certain embodiments, one or more of the tamper-respondent layers are divided into multiple, separate tamper-respondent circuit zones, with the tamper-respondent layers, including the circuit zones, being electrically connected to monitor circuitry within the secure volume.

Claims

1. A method of fabricating an electronic circuit comprising:

providing a multilayer circuit board, the multilayer circuit board being a single circuit board formed of multiple layers; and

disposing at least one electronic component on an uppermost surface of the multilayer circuit board, the multilayer circuit board including a continuous groove formed in the uppermost surface of the multilayered circuit board to facilitate attaching an enclosure to the multilayer circuit board, the at least one electronic component being within a surface area of the uppermost surface encircled by the continuous groove;

providing a tamper-respondent sensor embedded within the multilayer circuit board, the tamper-respondent sensor defining, at least in part, a secure volume associated with the multilayer circuit board, and comprising;

multiple tamper-respondent layers within the multilayer circuit board, the multiple tamper-respondent layers being spaced apart, parallel layers within the multilayer circuit board that facilitate defining the secure volume, at least in part, within the multilayer circuit board, and the multiple tamper-respondent layers comprising;

at least one tamper-respondent picture frame-type layer encircling the secure volume within the multilayer circuit board and disposed below the surface area of the multilayer circuit board encircled by the continuous groove, a tamper-respondent picture frame-type layer of the at least one tamper-respondent picture frame-type layer comprising one or more conductive trace lines extending horizontally around the tamper-respondent picture frame-type layer within the multilayer circuit board and encircling the secure volume within the multilayer circuit board; and

at least one tamper-respondent mat layer forming a base of the secure volume within the multilayer circuit board, the at least one tamper-respondent frame layer being disposed over the at least one tamper-respondent mat layer.

2. The method of claim 1, wherein at least one tamper-respondent layer of the multiple tamper-respondent layers comprises multiple, separate tamper-respondent circuit zones, and wherein the multiple tamper-respondent layers, including the multiple, separate tamper-respondent circuit zones of the at least one tamper-respondent layer, are electrically connected to monitor circuitry within the secure volume associated with the multilayer circuit board.

3. The method of claim 1, wherein at least two tamper-respondent layers of the multiple tamper-respondent layers each comprise multiple, separate tamper-respondent circuit zones, and wherein at least two tamper-respondent circuit zones within different tamper-respondent layers of the at least two tamper-respondent layers are electrically connected to a common monitor circuit within the secure volume associated with the multilayer circuit board.

4. The method of claim 3, wherein the at least one tamper-respondent picture frame-type layer of the multiple tamper-respondent layers defines, at least in part, a side portion of the secure volume within the multilayer circuit board.

5. The method of claim 1, wherein the multilayer circuit board comprises an external signal layer embedded within the multilayer circuit board, the external signal layer electrically connecting to the at least one electronic component disposed on the multilayer circuit board within the secure volume, and residing, at least in part, over a tamper-respondent mat layer of the at least one tamper-respondent mat layer.

6. The method of claim 1, wherein the multiple tamper-respondent layers within the multilayer circuit board comprise at least two tamper-respondent picture frame-type layers, the at least two tamper-respondent picture frame-type layers defining, at least in part, a periphery of the secure volume where extending into the multilayer circuit board.

7. The method of claim 1, wherein the at least one tamper-respondent picture frame-type layer embedded within the multilayer circuit board defines a periphery of the secure volume within the multilayer circuit board.

8. The method of claim 1, wherein the one or more conductive trace lines of the tamper-respondent picture frame-type layer of the at least one tamper-respondent picture frame-type layer encircling the secure volume within the multilayer circuit board are encircled or intersected by the continuous groove in the uppermost surface of the multilayer circuit board.

9. The method of claim 8, wherein the tamper-respondent mat layer of the at least one tamper-respondent may layer extends from below the secure volume outward past the groove in the multilayer circuit board.