Memory apparatus for in-chip error correction

• US 10,379,939 B2
• Filed: 03/27/2017
• Issued: 08/13/2019
• Est. Priority Date: 01/04/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Malladi, Krishna T., Zheng, Hongzhong
• Primary Examiner(s): Nguyen, Thien
• Application Number:
  US15/470,657
• Publication Number:
  US 20180189132A1
• Time in Patent Office: 869 Days
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/74 using duplex memories, i.e. using dual copies

Abstract

A method of performing memory deduplication and single error correction double error detection (SEC-DED) in a computer memory, the method including reading data from an array of memory chips, calculating at least one hash based on the data, checking the one or more hashes against at least one of a physical line ID hash and against a secondary hash, determining whether an error is detected, when an error is detected, correcting the data by changing each bit of the array of the memory chips one at a time until no error is detected, wherein between changing each bit, at least one hash is calculated based on the changed data, and the one or more hash for the new data is compared against one or more of a physical line ID hash and against a secondary hash, and again determining whether an error is detected, and outputting the corrected data when no error is detected.

Claims

1. A method of reducing access latency and improving data integrity by performing memory deduplication and single error correction double error detection (SEC-DED) in a computer memory, the method comprising:

reading, by a processor on a memory chip, data from an array of memory chips;

calculating, by the processor, one or more hashes based on the data;

checking, by the processor, the one or more hashes against a physical line ID hash to determine whether the one or more hashes matches the physical line ID hash;

detecting, by the processor, an error based on the one or more hashes being different from the physical line ID hash;

correcting, by the processor, the error by sequentially flipping a data value of each bit, for up to all bits, of the array of the memory chips by performing a write operation using error-correcting code (ECC) to generate changed data until no error is detected;

after flipping the data value of a respective bit of the bits, calculating, by the processor, at least one hash based on the changed data, and comparing the at least one hash based on the changed data against the physical line ID hash to determine whether the at least one hash matches the physical line ID hash;

accepting, by the processor, the changed data as corrected data when the at least one hash matches the physical line ID hash; and

outputting, by the processor, the corrected data.

2. The method of claim 1, wherein the data comprises eight bytes.

3. The method of claim 1, wherein the array of memory chips comprises 4-bit memory chips.

4. The method of claim 1, wherein the array of memory chips comprises sixteen memory chips.

5. The method of claim 1, wherein a total number of bits in the array is sixty-four.

6. The method of claim 1, wherein the physical line ID hash comprises a 16-bit hash.

7. The method of claim 1, further comprising:

detecting an uncorrectable memory error by determining more than one chip of the array of memory chips contain a data error as the error during a read operation; and

using pins of an ECC chip to convey an uncorrectable memory error to a CPU.

8. The method of claim 1, further comprising:

detecting an uncorrectable memory error by determining more than one chip of the array of memory chips contain a data error as the error during a read operation; and

sending a bus signal on an SMBus to convey an uncorrectable memory error as the error to a memory host.

9. A method of reducing access latency and improving data integrity by performing memory deduplication and a single chipkill mechanism in a computer memory, the method comprising:

reading data, by a processor on a memory chip, from an array of memory chips;

calculating, by the processor, one or more hashes based on the data;

checking, by the processor, the one or more hashes against a physical line ID hash to determine whether the one or more hashes matches the physical line ID hash;

detecting, by the processor, an error based on the one or more hashes being different from the physical line ID hash;

correcting, by the processor, the error by sequentially flipping a data value of each bit, for up to all bits, of each memory chip of the array of the memory chips for up to all of the memory chips by performing a write operation using error-correcting code (ECC) to generate changed data until no error is detected;

after flipping the data value of a respective bit of the bits, calculating, by the processor, at least one hash based on the changed data, and comparing the at least one hash based on the changed data against the physical line ID hash to determine whether the at least one hash matches the physical line ID hash;

accepting, by the processor, the changed data as corrected data when the at least one hash matches the physical line ID hash; and

outputting, by the processor, the corrected data.

10. The method of claim 9, wherein the data comprises eight bytes.

11. The method of claim 9, wherein the array of memory chips comprises 4-bit memory chips.

12. The method of claim 9, wherein the array of memory chips comprises sixteen memory chips.

13. The method of claim 9, wherein a total number of bits in the array is sixty-four.

14. The method of claim 9, wherein the physical line ID hash comprises a 16-bit hash.

15. A method of reducing access latency and improving data integrity by performing memory deduplication and a double chipkill mechanism in a computer memory, the method comprising:

reading, by a processor on a memory chip, data from an array of memory chips;

calculating, by the processor, one or more hashes based on the data;

checking, by the processor, the one or more hashes against a physical line ID hash to determine whether the one or more hashes matches the physical line ID hash;

detecting, by the processor, an error based on the one or more hashes being different from the physical line ID hash;

correcting, by the processor, the error by sequentially flipping a data value of each bit, for up to all bits, of each pair of memory chips of the array of memory chips for up to all possible pairs of memory chips of the array of the memory chips by performing a write operation using error-correcting code (ECC) to generate changed data until no error is detected;

after flipping the data value of a respective bit of the bits, calculating, by the processor, at least one hash based on the changed data, and comparing the at least one hash based on the changed data against the physical line ID hash to determine whether the at least one hash matches the physical line ID hash;

accepting, by the processor, the changed data as corrected data when the at least one hash matches the physical line ID hash; and

outputting, by the processor, the corrected data.

16. The method of claim 15, wherein the data comprises eight bytes.

17. The method of claim 15, wherein the array of memory chips comprises 4-bit memory chips.

18. The method of claim 15, wherein the array of memory chips comprises sixteen memory chips.

19. The method of claim 15, wherein a total number of bits in the array is sixty-four.