Processor core to coprocessor interface with FIFO semantics

• US 10,380,058 B2
• Filed: 09/06/2016
• Issued: 08/13/2019
• Est. Priority Date: 09/06/2016
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Brown, David A., Fowler, Daniel, Jain, Rishabh, Schlanger, Erik, Duller, Michael
• Primary Examiner(s): Shin, Christopher B
• Application Number:
  US15/256,936
• Publication Number:
  US 20180067889A1
• Time in Patent Office: 1,071 Days
• Field of Search: 710105
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Techniques are provided for exchanging dedicated hardware signals to manage a first-in first-out (FIFO). In an embodiment, a first processor initiates content transfer into the FIFO. The first processor activates a first hardware signal that is reserved for indicating that content resides within the FIFO. A second processor activates a second hardware signal that is reserved for indicating that content is accepted. The second hardware signal causes the first hardware signal to be deactivated. This exchange of hardware signals demarcates a FIFO transaction, which is mediated by interface circuitry of the FIFO.

Claims

1. A method comprising:

sending, by a first processor, a first hardware signal that indicates that content is available for appending onto a first-in first-out (FIFO);

in response to said sending said first hardware signal, transferring said content from a memory that is shared by said first processor and a second processor into said FIFO;

after said transferring said content, sending, by said second processor, a second hardware signal that indicates that said content is transferred into said FIFO;

wherein said second hardware signal causes said first hardware signal to terminate.

2. The method of claim 1 wherein:

said first processor is a processing core of a central processing unit (CPU);

said second processor is a coprocessor that is connected to said CPU.

3. The method of claim 1 further comprising blocking execution of said first processor while at least one condition occurs of:

said FIFO has insufficient capacity to receive content, or

a hardware signal is active.

4. The method of claim 1 wherein:

said first processor is a first coprocessor that is connected to a CPU;

said second processor is one of;

a) a second coprocessor that is connected to said CPU, or b) a processing core of said CPU.

5. The method of claim 1 wherein said FIFO comprises at least one of:

a synchronous FIFO or a circular buffer.

6. The method of claim 1 further comprising

blocking execution of said second processor while said FIFO is empty.

7. The method of claim 1 wherein said FIFO is contained within at least one of:

a coprocessor, a system on a chip (SoC), or less than an entire random access memory (RAM).

8. The method of claim 1 wherein said content comprises at least one of:

a memory pointer, a descriptor, or a unit of work.

9. The method of claim 1 wherein a capacity of said FIFO is software configurable or logically unbounded.

10. The method of claim 1 further comprising said second processor performing at least one of:

entering a low-power mode until said FIFO contains content, or

blocking execution of said second processor until said FIFO contains an amount of content that exceeds a software-configurable threshold.

11. The method of claim 1 further comprising:

sending, by said first processor, a third hardware signal that indicates that content is available for appending onto a second FIFO;

after said transferring said content, sending, by said second processor, a fourth hardware signal that indicates that said content is transferred into said second FIFO.

12. One or more non-transitory computer-readable media storing instructions that, when executed by one or more processors, cause:

sending, by a first processor, a first hardware signal that indicates that content is available for appending onto a first-in first-out (FIFO);

in response to said sending said first hardware signal, transferring said content from a memory that is shared by said first processor and a second processor into said FIFO;

after said transferring said content, sending, by said second processor, a second hardware signal that indicates that said content is transferred into said FIFO;

wherein said second hardware signal causes said first hardware signal to terminate.

13. The one or more non-transitory computer-readable media of claim 12 wherein:

said first processor comprises a central processing unit (CPU);

said second processor comprises a coprocessor of said CPU.

14. The one or more non-transitory computer-readable media of claim 12 wherein:

said first processor comprises a first coprocessor of a CPU;

said second processor comprises a second coprocessor of said CPU.

15. The one or more non-transitory computer-readable media of claim 12 wherein said instructions further cause:

blocking execution of said second processor while said FIFO is empty.

16. The one or more non-transitory computer-readable media of claim 12 wherein the instructions further cause blocking execution of said first processor while a hardware signal is active.

17. The one or more non-transitory computer-readable media of claim 12 wherein said FIFO is contained within at least one of:

a coprocessor or less than an entire random access memory (RAM).

18. The one or more non-transitory computer-readable media of claim 12 wherein said content comprises at least one of:

a memory pointer, a descriptor, or a unit of work.

19. The one or more non-transitory computer-readable media of claim 12 wherein a capacity of said FIFO is software configurable or logically unbounded.

20. The one or more non-transitory computer-readable media of claim 12 wherein said instructions further cause at least one of:

said second processor entering a low-power mode until said FIFO contains content, or

blocking execution of said second processor until said FIFO contains an amount of content that exceeds a software-configurable threshold.