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Processor core to coprocessor interface with FIFO semantics

  • US 10,380,058 B2
  • Filed: 09/06/2016
  • Issued: 08/13/2019
  • Est. Priority Date: 09/06/2016
  • Status: Active Grant
First Claim
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1. A method comprising:

  • sending, by a first processor, a first hardware signal that indicates that content is available for appending onto a first-in first-out (FIFO);

    in response to said sending said first hardware signal, transferring said content from a memory that is shared by said first processor and a second processor into said FIFO;

    after said transferring said content, sending, by said second processor, a second hardware signal that indicates that said content is transferred into said FIFO;

    wherein said second hardware signal causes said first hardware signal to terminate.

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