Low-pincount high-bandwidth memory and memory bus

• US 10,380,060 B2
• Filed: 06/09/2017
• Issued: 08/13/2019
• Est. Priority Date: 06/17/2016
• Status: Active Grant

• Current Assignee: Etron Technology America Incorporated (Etron Technology Inc), Etron Technology Inc
• Original Assignee: Etron Technology Inc
• Inventors: Crisp, Richard Dewitt
• Primary Examiner(s): Abad, Farley
• Assistant Examiner(s): Yu, Henry W
• Application Number:
  US15/618,907
• Publication Number:
  US 20170364469A1
• Time in Patent Office: 795 Days
• Field of Search: 710 4- 5, 710 20- 21, 710 35, 710308
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport. The physical layout of one version of the memory IC dispatches switching signal terminals adjacent to one short edge of the memory die to minimize the die area overhead for controller IC memory interface circuitry when used in a stacked die multi-chip package with said memory controller IC. The memory IC interface signal placement and signal count minimize signal length and circuitry for the memory bus signals.

Claims

1. A bus configured to interconnect at least one memory storage integrated circuit (IC) to a controller IC, the bus comprising:

a plurality of electrical bus conductors configured to be electrically coupled to a collection of terminals on the memory IC and to corresponding terminals on the controller IC,

wherein the bus conductors are categorized in one or more of the following groups based on a type of signal transmitted through the bus conductor;

a data bus group, a data strobe group, a clock group, a chip select group or a control group,

wherein the one or more bus conductors in the data bus group are adapted to transport a parallel command from the controller IC to the memory IC during a command transfer time and are further adapted to transport data between the memory IC and the controller IC using a burst mode during a data transfer time, and

wherein the one or more bus conductors in the control group comprise a single conductor adapted to transport a serial command from the controller IC to the memory IC during the data transfer time such that the serial command can direct the operation of the memory IC by providing address and data transfer control information to the memory IC.

2. The bus of claim 1, wherein the serial command includes an operation code specifying a function of the serial command, the function being one of a null operation function, a burst mode function, an activation function or a utility function, wherein the utility function includes means to command the memory IC to terminate an ongoing burst mode memory operation and includes means to command the memory IC to precharge banks contained therein.

3. The bus of claim 2, wherein the bus can transport a first serial command from the controller IC to the memory IC and immediately thereafter transport a second serial command to the memory IC.

4. The bus of claim 3, wherein the serial command provides for switching the bus operating mode between read mode and write mode and between write mode and read mode while the memory IC is performing a burst memory operation.

5. The bus of claim 1, wherein a width of the data bus is one byte, where a byte is a one of eight or nine bits, and wherein the data strobe group comprises two conductors.

6. The bus of claim 1, wherein a width of the data bus is two bytes, where a byte is a one of eight or nine bits, and wherein the data strobe group comprises two conductors.

7. The bus of claim 1, wherein a width of the data bus is two bytes, where a byte is a one of eight or nine bits, and where the data strobe group comprises four conductors.

8. The bus of claim 1, wherein a width of the data bus is four bytes, where a byte is a one of eight or nine bits, and where the data strobe group comprises eight conductors.

9. The bus of claim 1, wherein a width of the data bus is six bytes, where a byte is a one of eight or nine bits, and where the data strobe group comprises twelve conductors.

10. The bus of claim 1, wherein a width of the data bus is eight bytes, where a byte is a one of eight or nine bits, and where the data strobe group comprises sixteen conductors.

11. The bus of claim 1, wherein a write mask is transferred over the data bus as part of a burst write operation.

12. The bus of claim 4, wherein the bus is adapted to operate in a sustained burst mode of unlimited duration.

13. The bus of claim 12, wherein the bus is disposed within a single semiconductor package containing a controller IC die and a memory IC die, wherein the memory IC die and controller IC die are disposed in a stacked arrangement, wherein the bus conductors comprise a group of unique bondwires, with each bus interface terminal on the memory IC die coupled via a unique bondwire to the corresponding bus interface terminal on the memory controller IC die, and a backside of the memory IC die faces a frontside of the controller IC die.

14. The bus of claim 12, wherein the bus is disposed within a single semiconductor package containing a controller IC die and a memory IC die, wherein the controller IC die'"'"'s bus terminals are coupled to metallic conductors disposed on a substrate using flip-chip technology wherein the memory IC die is disposed in a stacked die arrangement with the controller IC die such that an active face of the memory IC die faces away from the substrate and such that each bus conductor is comprised of a series combination of a bondwire and substrate metallic conductor adapted such that each bus interface terminal of the controller IC is electrically coupled to a first end of a unique substrate metallic conductor and where the second end of each unique substrate metallic conductor trace is electrically coupled via a unique wirebond to the corresponding bus interface terminal on the memory IC die such that each bus interface terminal of the memory IC is coupled to the corresponding bus interface terminal of the controller IC via a series connection of at least a unique bondwire and a unique conductor disposed on the substrate.

15. The bus of claim 12, wherein the memory IC and the controller IC are each disposed in individual packages, with the bus interface terminals of each IC electrically coupled to external bus terminals on an outside of each package and wherein the bus conductors are comprised of a group of individual conductors disposed on the substrate such that each external bus interface terminal of the memory IC is coupled to a first end of a unique one of the group of individual conductors disposed on the substrate wherein the second end of the individual conductor is coupled to the corresponding external bus interface terminal of the controller IC in such a way that each bus interface terminal of the memory IC is coupled to the corresponding bus interface terminal of the controller IC via unique individual conductors disposed on the substrate.

16. The bus of claim 12, wherein the memory IC and the controller IC are each disposed in individual packages, wherein the bus interface terminals of each IC are electrically coupled to external bus interface terminals on an outside of each package and the memory IC package is disposed on the controller IC package in such a way that the bus conductors include solder connections electrically coupling each bus interface external terminal of the memory IC package to the corresponding external bus interface terminal of the controller IC package in a package-on-package stacking configuration.

17. The bus of claim 12, wherein the bus conductors are comprised of a group of unique wirebonds, each electrically coupling a bus interface terminal of the controller IC die to the corresponding bus interface terminal of the memory IC die, such that each memory IC bus interface terminal is coupled to the corresponding bus interface terminal of the controller IC wherein the memory IC die and the controller IC die are disposed adjacent to one another in a common plane on a substrate with a backside of each die facing the substrate.

18. The bus of claim 12, wherein a memory IC die and a controller IC die are each disposed on a common substrate where a backside of each die faces the substrate, and where each bus interface terminal of the memory IC die has a wirebond electrically coupling it to a first end of a unique metallic conductor disposed on the substrate and where the second end of the metallic conductor has a wirebond electrically coupling it to the corresponding bus interface terminal of the controller die in such a way that each bus interface terminal on the memory IC is electrically coupled to the corresponding bus interface terminal on the controller IC wherein each bus conductor comprises an electrical circuit consisting of a series combination of a unique first bondwire, a unique substrate conductor and a unique second bondwire.

19. The bus of claim 12, wherein the controller IC die and the memory IC die are each disposed with the active surface facing a flip chip substrate and with bus interface terminals electrically coupled to metallic conductors disposed thereon using flip chip technology such that each bus interface terminal on the memory IC die is electrically coupled to the corresponding bus interface terminal on the controller IC die with a unique conductor disposed on the flip chip substrate wherein the substrate conductors comprise the bus conductors.

20. The bus of claim 12, wherein the memory interface terminals of the memory IC die are each electrically coupled via bus conductors to the corresponding memory interface terminals on the memory controller IC die such that the bus conductors comprise metallic conductors disposed in channels that pass through at least a one of the two die.

21. The bus of claim 12, wherein the bus conductors comprise metallic bumps disposed on the bus interface terminals on a one of the memory IC die and the controller IC die such that at least one unique metallic bump electrically couples each bus interface terminal of the memory IC die with the corresponding bus interface terminal on the memory controller IC wherein the active surfaces of both die face one another.

22. A bus for interconnecting at least one memory IC with a controller IC wherein the bus is adapted to transfer memory commands and data using the same conductors wherein the bus is comprised of 16 conductors adapted to transport memory commands and data, two conductors adapted to transport clocks, and no more than five additional conductors adapted to transport data strobe and memory control signals and where the bus is adapted to transfer data at a peak bandwidth of at least 3000 Megabytes per second, wherein a single conductor is adapted to transport, from the controller IC to the memory IC concurrent with the transfer of data, a serial command that can direct the operation of the memory IC by providing address and data transfer control information to the memory IC.

23. A means for interconnecting at least one memory storage integrated circuit (IC) to a controller IC, comprising:

means for electrically coupling a collection of terminals on the memory IC to corresponding terminals on the controller IC, including means for transmitting signals of one or more of the following type;

data signals, indications of stability of transmitted information, clock signals, chip selection signals, or control signals, and

means for transmitting through a single pin a serial command from the controller IC to the memory IC during a data transfer time such that the serial command can direct the operation of the memory IC by providing address and data transfer control information to the memory IC.