Method of manufacturing semiconductor device with interlayer insulating layers

• US 10,381,265 B2
• Filed: 05/08/2017
• Issued: 08/13/2019
• Est. Priority Date: 05/31/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Min, Sun-ki, Ryu, Koung-min, Kim, Sung-soo, Kang, Sang-koo
• Primary Examiner(s): Tran, Thanh Y.
• Application Number:
  US15/589,169
• Publication Number:
  US 20170345712A1
• Time in Patent Office: 827 Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of manufacturing a semiconductor device includes forming first and second pattern structures on first and second regions of a substrate, respectively, forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region, forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including a first colloid, and converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming first and second pattern structures on first and second regions of a substrate, respectively;

forming a preparatory first interlayer insulating layer covering the first pattern structure on the first region;

forming a preparatory second interlayer insulating layer covering the second pattern structure on the second region, the preparatory second interlayer insulating layer including a first colloid; and

converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers,

wherein the preparatory first interlayer insulating layer comprises a second colloid different from the first colloid,

wherein each of the first colloid and the second colloid comprises a dispersoid and a dispersion medium surrounding the dispersoid, and

wherein a material of the dispersion medium of the first colloid is the same as a material of the dispersion medium of the second colloid.

2. The method of claim 1, wherein a density of the second interlayer insulating layer is higher than a density of the first interlayer insulating layer.

3. The method of claim 1, further comprising:

after converting the preparatory first and second interlayer insulating layers into the first and second interlayer insulating layers, respectively,

planarizing the first and second interlayer insulating layers to have upper surfaces thereof lower than upper surfaces of the first and second pattern structures; and

forming a third interlayer insulating layer covering the upper surfaces of the first and second interlayer insulating layers and side surfaces of the first and second pattern structures,

wherein a level of the upper surface of the first interlayer insulating layer is the same as a level of the upper surface of the second interlayer insulating layer.

4. The method of claim 3, wherein

the first pattern structure and the second pattern structure include a plurality of first pattern structures and a plurality of second pattern structures, respectively,

a first pattern density of the plurality of first pattern structures is higher than a second pattern density of the plurality of second pattern structures, or

a first space between adjacent first pattern structures is smaller than a second space between adjacent second pattern structures.

5. The method of claim 1, wherein

a density of the first interlayer insulating layer formed by annealing the preparatory first interlayer insulating layer is lower than a density of the second interlayer insulating layer.

6. The method of claim 1, wherein

a concentration of the second colloid is lower than a concentration of the first colloid.

7. The method of claim 1, wherein

each of the first and second regions comprises fins protruding from an upper surface of the substrate and extending in one direction, and

the first and second pattern structures intersect the fins in the first and second regions, respectively.

8. The method of claim 1, wherein

the first and second pattern structures include first and second dummy gate structures, respectively,

before annealing the preparatory first and second interlayer insulating layers, a first opening of the preparatory first interlayer insulating layer delimiting the first dummy gate structure has the same shape as a second opening of the preparatory second interlayer insulating layer delimiting the second dummy gate structure, and

after annealing the preparatory first and second interlayer insulating layers, the first and second openings are modified to have different shapes.

9. The method of claim 8, further comprising:

after annealing the preparatory first and second interlayer insulating layers, forming first and second gate structures in the modified first and second openings, respectively,

wherein a width of the second gate structure is smaller than a width of the first gate structure.

10. The method of claim 8, further comprising:

after annealing the preparatory first and second interlayer insulating layers, forming first and second gate structures in the modified first and second openings, respectively,

wherein an inclination of side surfaces of the first gate structure is different from an inclination of side surfaces of the second gate structure.

11. The method of claim 1, wherein

a concentration of the second colloid is lower than a concentration of the first colloid, or a thermal expansivity of the second colloid is lower than a thermal expansivity of the first colloid.

12. The method of claim 1, wherein the first and second pattern structures include first and second dummy gate structures, respectively, and the second dummy gate structure includes a plurality of second dummy gate structures,

the method further including, after annealing the preparatory first and second interlayer insulating layers,

forming an opening exposing the substrate by removing at least one of the plurality of second dummy gate structures;

forming a device isolation trench by etching the substrate exposed by the opening; and

forming a device isolation structure by filling the device isolation trench and the opening.

13. The method of claim 12, wherein the device isolation structure comprises the same material as a dispersion medium of the preparatory second interlayer insulating layer.

14. A method of manufacturing a semiconductor device, the method comprising:

forming a preparatory first interlayer insulating layer on a first region of a substrate, the preparatory first interlayer insulating layer delimiting a first pattern structure;

forming a preparatory second interlayer insulating layer on a second region of the substrate, the preparatory second interlayer insulating layer delimiting a second pattern structure and including a first colloid; and

converting the preparatory first and second interlayer insulating layers into first and second interlayer insulating layers, respectively, by annealing the preparatory first and second interlayer insulating layers,

wherein at least one of a density and a thermal expansivity of the second interlayer insulating layer is higher than at least one of a density and a thermal expansivity, respectively, of the first interlayer insulating layer, and

wherein the preparatory first interlayer insulating layer comprises a second colloid different from the first colloid,

wherein the first colloid includes a dispersion medium and a dispersoid surrounding the dispersion medium,

wherein a material of the dispersion medium is the same as a material of the preparatory first interlayer insulating layer,

wherein a material of the dispersion medium of the first colloid is the same as a material of the dispersion medium of the second colloid.

15. A method comprising:

forming a pattern structure on a substrate, the pattern structure including a first pattern structure and a second pattern structure, a pattern density of the second pattern structure being lower than a pattern density of the first pattern structure;

forming a preparatory first interlayer insulating layer on the first pattern structure, the preparatory first interlayer insulating layer including a second colloid;

forming a first interlayer insulating layer on the first pattern structure;

forming a preparatory second interlayer insulating layer on the second pattern structure, the preparatory second interlayer insulating layer including a first colloid, the second colloid different from the first colloid;

annealing the preparatory first interlayer insulating layer and the preparatory second interlayer insulating layer to form a second interlayer insulating layer; and

planarizing the first and second interlayer insulating layers to have upper surfaces thereof lower than upper surfaces of the first and second pattern structures,

wherein a level of the upper surface of the first interlayer insulating layer is the same as a level of the upper surface of the second interlayer insulating layer,

wherein each of the first colloid and the second colloid comprises a dispersoid and a dispersion medium surrounding the dispersoid, and

wherein a material of the dispersion medium of the first colloid is the same as a material of the dispersion medium of the second colloid.

16. The method of claim 15, further comprising:

forming a third interlayer insulating layer on the upper surfaces of the first and second interlayer insulating layers,

wherein the second interlayer insulating layer has substantially the same etching rate as the first interlayer insulating layer.

17. The method of claim 15, wherein a concentration of the second colloid is lower than a concentration of the first colloid, or a thermal expansivity of the second colloid is lower than a thermal expansivity of the first colloid.