Method for producing a plurality of measurement regions on a chip, and chip with measurement regions

• US 10,381,277 B2
• Filed: 06/21/2017
• Issued: 08/13/2019
• Est. Priority Date: 05/30/2013
• Status: Active Grant

• Current Assignee: Boehringer Ingelheim Vetmedica GmbH (C.H. Boehringer Sohn AG & Co. KG)
• Original Assignee: Boehringer Ingelheim Vetmedica GmbH (C.H. Boehringer Sohn AG & Co. KG)
• Inventors: Schieber, Markus, Schoeder, Heinz
• Primary Examiner(s): Garber, Charles D
• Assistant Examiner(s): Imtiaz, S M Sohel
• Application Number:
  US15/629,006
• Publication Number:
  US 20170301593A1
• Time in Patent Office: 783 Days
• CPC Class Codes: B01J 2219/00317 Microwell devices, i.e. having large numbers of wells
• CPC Class Codes: B01J 2219/00619 using hydrophilic or hydrophobic regions
• CPC Class Codes: B01J 2219/00635 by reactive plasma treatment
• CPC Class Codes: B01J 2219/00637 by coating it with another layer
• CPC Class Codes: B01J 2219/00653 the compounds being bound to electrodes embedded in or on the solid supports
• CPC Class Codes: B01L 2200/12 Specific details about manufacturing devices
• CPC Class Codes: B01L 2300/0645 Electrodes
• CPC Class Codes: B01L 2300/0819 Microarrays; Biochips
• CPC Class Codes: B01L 2300/0861 Configuration of multiple channels and/or chambers in a single devices
• CPC Class Codes: B01L 2300/0887 Laminated structure
• CPC Class Codes: B01L 3/5088 confining liquids at a location by surface tension, e.g. virtual wells on plates, wires B01L3/50857 takes precedence
• CPC Class Codes: G01N 27/403 Cells and electrode assemblies
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes

Abstract

A chip and a method for producing the chip with a plurality of measurement regions which are provided with electrodes for electrically detecting reactions in which, in order to reliably separate the individual measurement regions from one another, a monolayer of a fluorosilane is formed on the chip surface which has strongly hydrophobic properties. Therefore, during spotting with a liquid, the drops of liquid applied by spotting can be reliably prevented from coalescing, and thus, causing mixing of the substances in the drops of liquid which are supposed to be immobilized in the measurement regions.

Claims

1. A chip comprising a plurality of electrically addressable measurement regions, wherein a compartmental structure separates the measurement regions from one another on the chip surface, wherein the compartmental structure is formed from a self-assembling hydrophobic monolayer of a silane compound which covers the chip surface outside the measurement regions

wherein the measurement regions have hydrophilic properties,

wherein the measurement regions have an average diameter of more than 100 μ

m and less than 500 μ

m,

wherein the compartmental structure is smaller in height than in width, and

wherein the width of the compartmental structure between two adjacent measurement regions is greater than the height of the compartmental structure relative to the chip surface carrying the measurement regions by at least a factor 5.

2. The chip according to claim 1, wherein the chip surface is planar and the compartmental structure is raised relative thereto.

3. The chip according to claim 1, wherein electrically contactable electrode pairings are structured in each of the measurement regions on the chip.

4. The chip according to claim 1, wherein the compartmental structure surrounds each measurement region completely or annularly with a hydrophobic layer or a hydrophobic intermediate region.

5. The chip according to claim 1, wherein the compartmental structure or hydrophobic layer or monolayer is of lattice-shaped and/or honeycomb-shaped configuration.

6. The chip according to claim 1, wherein the hydrophobic layer is configured as a flat coating.

7. The chip according to claim 1, wherein the height of the compartmental structure is more than 10 nm and less than 2 μ

m.

8. The chip according to claim 1, wherein the compartmental structure or hydrophobic layer or monolayer forms hydrophobic intermediate regions between the measurement regions.

9. The chip according to claim 8, wherein the intermediate regions between the measurement regions have a width between the measurement regions of more than 20%, of a measurement region.

10. The chip according to claim 8, wherein the intermediate regions have a width between the measurement regions of more than 5 μ

m.

11. The chip according to claim 1, wherein the compartmental structure or the hydrophobic layer or monolayer has a contact angle with water of at least 90°

.

12. The chip according to claim 1, wherein the compartmental structure is formed from the self-assembling monolayer of a fluorosilane compound.

14. The chip of claim 1, wherein the width of the compartmental structure between two adjacent measurement regions is greater than the height of the compartmental structure relative to the chip surface carrying the measurement regions by at least a factor 10.

13. A method for producing a chip having a plurality of electrically addressable measurement regions or for producing a plurality of measurement regions on a chip, comprising:

structuring electrically contactable electrode pairings on the chip in each of the electrically addressable measurement regions, the measurement regions being formed by producing a compartmental structure which separates the measurement regions from one another, and

producing hydrophobic wetting properties on a chip surface outside of the measurement regions

wherein the compartmental structure is formed from the self-assembling hydrophobic monolayer of a silane compound which covers the chip surface outside of the measurement regions, and

producing hydrophilic properties in the measurement regions

wherein the measurement regions have an average diameter of more than 100 μ

m and less than 500 μ

m,

wherein the compartmental structure is smaller in height than in width, and

wherein the width of the compartmental structure between two adjacent measurement regions is greater than the height of the compartmental structure relative to the chip surface carrying the measurement regions by at least a factor 5.

15. The method of claim 13, wherein the width of the compartmental structure between two adjacent measurement regions is greater than the height of the compartmental structure relative to the chip surface carrying the measurement regions by at least a factor 10.