Semiconductor device and structure
First Claim
Patent Images
1. A 3D semiconductor device, comprising:
- a first die comprising first transistors and first interconnect, overlaid by a second die comprising second transistors and second interconnect,wherein said first die has a first die area and said second die has a second die area,wherein said first die area is at least 10% larger than said second die area,wherein said second die is aligned to said first die with less than 400 nm alignment error, andwherein said second die comprises at least two alignment marks.
1 Assignment
0 Petitions
Accused Products
Abstract
A 3D semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, and where the second die has a thickness of less than four microns.
903 Citations
20 Claims
-
1. A 3D semiconductor device, comprising:
-
a first die comprising first transistors and first interconnect, overlaid by a second die comprising second transistors and second interconnect, wherein said first die has a first die area and said second die has a second die area, wherein said first die area is at least 10% larger than said second die area, wherein said second die is aligned to said first die with less than 400 nm alignment error, and wherein said second die comprises at least two alignment marks. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A 3D semiconductor device, comprising:
-
a first die comprising first transistors and first interconnect, overlaid by a second die comprising second transistors and second interconnect, wherein said first die is sourced from a first wafer with a diameter greater than 280 mm and said second die is sourced from a second wafer with a diameter less than 240 mm, wherein said second die is aligned to said first die with less than 400 nm alignment error, and wherein said second die comprises at least two alignment marks. - View Dependent Claims (8, 9, 10, 11, 12, 13)
-
-
14. A 3D semiconductor device, comprising:
a first die comprising first transistors and first interconnect, overlaid by a second die comprising second transistors and second interconnect, wherein said first die has a first die area and said second die has a second die area, wherein said first die area is at least 10% larger than said second die area, and wherein said second die comprises at least two alignment marks positioned close to said second die edge, wherein said second die is aligned to said first die with less than 400 nm alignment error, and wherein said second die has a thickness of less than four microns. - View Dependent Claims (15, 16, 17, 18, 19, 20)
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeMonolithic 3D, Inc.
-
Original AssigneeMonolithic 3D, Inc.
-
InventorsOr-Bach, Zvi
-
Primary Examiner(s)Lee, Calvin
-
Application NumberUS15/632,325Publication NumberTime in Patent Office780 DaysField of Search438108, 438109, 257686US Class CurrentCPC Class CodesH01L 2223/5442 comprising non digital, non...H01L 2223/54426 for alignmentH01L 2225/06541 Conductive via connections ...H01L 2225/06568 the devices decreasing in s...H01L 2225/06593 Mounting aids permanently o...H01L 23/544 Marks applied to semiconduc...H01L 25/0652 the devices being arranged ...H01L 25/0657 Stacked arrangements of dev...H01L 25/074 Stacked arrangements of non...H01L 25/0756 Stacked arrangements of dev...H01L 25/50 Multistep manufacturing pro...
