Semiconductor device

• US 10,381,370 B2
• Filed: 01/12/2018
• Issued: 08/13/2019
• Est. Priority Date: 11/08/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Shin, Yoo-cheol, Park, Young-woo, Lee, Jae-duk
• Primary Examiner(s): Bradford, Peter
• Application Number:
  US15/869,888
• Publication Number:
  US 20180138192A1
• Time in Patent Office: 578 Days
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

Claims

1. A semiconductor device comprising:

a first driving circuit region and a second driving circuit region on a first substrate to generate driving signals;

a second substrate on the first and second driving circuit regions;

a memory cell array region on the second substrate, the memory cell array region entirely overlapping the first driving circuit region and not or partially overlapping the second driving circuit region;

a first upper interconnection layer on the memory cell array region; and

a first vertical contact through the memory cell array region and the second substrate, the first vertical contact connecting the first upper interconnection layer to the first driving circuit region.

2. The semiconductor device of claim 1, further comprising a second vertical contact through an interlayer insulating layer, wherein the second vertical contact electrically connects a second upper interconnection layer on the memory cell array region to the second driving circuit region.

3. The semiconductor device of claim 2, wherein the second vertical contact includes an interconnection contact that is not disposed through the memory cell array region and the second substrate and separated from the memory cell array region and the second substrate.

4. The semiconductor device of claim 1, wherein the second driving circuit region includes a row decoder circuit.

5. The semiconductor device of claim 1, further comprising a bonding pad region and the second substrate extends to the bonding pad region.

6. The semiconductor device of claim 5, wherein the bonding pad region does not overlap the second driving circuit region.

7. The semiconductor device of claim 1, wherein the second substrate includes a common source line.

8. The semiconductor device of claim 7, wherein the second substrate includes a semiconductor layer.

9. The semiconductor device of claim 7, wherein the second substrate includes a polysilicon layer.

10. The semiconductor device of claim 1, wherein the memory cell array region constitutes a vertical NAND memory.

11. The semiconductor device of claim 1, further comprising a memory cell array on the memory cell array region, wherein the memory cell array includes:

a channel layer extending in a vertical direction on the second substrate; and

at least one ground selection line, at least one word line, and at least one string selection line spaced apart in the vertical direction along a sidewall of the channel layer.

12. The semiconductor device of claim 11, wherein the channel layer directly contacts the second substrate.

13. The semiconductor device of claim 1, wherein the first driving circuit region includes at least one driving circuit.

14. The semiconductor device of claim 13, wherein the at least one driving circuit is to process input or output data.

15. The semiconductor device of claim 14, wherein the at least one driving circuit includes a page buffer, a latch circuit, a column decoder, a sense amplifier, or a data in/out circuit.

16. The semiconductor device of claim 1, wherein the first upper interconnection layer includes at least one of copper, aluminum, silver, or gold.

17. The semiconductor device of claim 1, further comprising a barrier metal layer between the first driving circuit region and the second substrate.