Semiconductor device and manufacturing method thereof

• US 10,381,375 B2
• Filed: 03/23/2018
• Issued: 08/13/2019
• Est. Priority Date: 07/17/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Choi, Kang Sik
• Primary Examiner(s): Smith, Zandra V
• Assistant Examiner(s): Stevenson, Andre C
• Application Number:
  US15/934,477
• Publication Number:
  US 20190019808A1
• Time in Patent Office: 508 Days
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A semiconductor device includes: a stack structure including horizontal conductive patterns and interlayer insulating layers, which are alternately stacked; gate patterns overlapping with both ends of the stack structure under the stack structure, the gate patterns being spaced apart from each other; and a channel pattern including vertical parts penetrating the stack structure, and a connection part disposed under the stack structure, the connection part connecting the vertical parts.

Claims

1. A semiconductor device comprising:

a stack structure including horizontal conductive patterns and interlayer insulating layers, which are alternately stacked in a first direction;

gate patterns overlapping with both ends of the stack structure under the stack structure, the gate patterns being spaced apart from each other in a second direction intersecting the first direction; and

a channel pattern including vertical parts penetrating the stack structure, and a connection part disposed under the stack structure, the connection part connecting the vertical parts,

wherein the connection part of the channel pattern faces a bottom surface of the stack structure between the gate patterns.

2. The semiconductor device of claim 1, wherein the gate patterns are formed of a conductive material different from that of the horizontal conductive patterns.

3. The semiconductor device of claim 1, wherein each of the gate patterns is formed thicker than each of the horizontal conductive patterns in the first direction.

4. The semiconductor device of claim 1, further comprising:

a well structure disposed under the gate patterns, the well structure extending to overlap with the stack structure under the stack structure, the well structure being disposed to be spaced apart from the gate patterns and the stack structure in the first direction, the well structure including a first conductivity type dopant; and

supporting poles supporting a space between the stack structure and the well structure under the stack structure, the supporting poles extending longer toward the well structure than the gate patterns.

5. The semiconductor device of claim 4, wherein the connection part of the channel pattern has a one-body structure that:

extends along the bottom surface of the stack structure from the vertical parts of the channel pattern;

extends along sidewalls of the supporting poles and the gate patterns from a portion along the bottom surface of the stack structure;

extends along bottom surfaces of the gate patterns from portions along the sidewalls of the gate patterns; and

extends along a top surface of the well structure from portions along the sidewalls of the supporting poles.

6. The semiconductor device of claim 5, wherein a second conductivity type dopant different from the first conductivity type dopant is distributed inside the connection part of the channel pattern, which extends along the bottom surfaces of the gate patterns.

7. The semiconductor device of claim 6, wherein the first conductivity type dopant is a p-type dopant, and

the second conductivity type dopant is an n-type dopant.

8. The semiconductor device of claim 5, wherein portions of the connection part of the channel pattern, which extends along the bottom surfaces of the gate patterns, are defined as first end parts,

wherein the first end parts protrude further laterally than sidewalls of the stack structure and the sidewalls of the gate patterns.

9. The semiconductor device of claim 5, wherein portions of the connection part of the channel pattern, which extends along the bottom surfaces of the gate patterns, are defined as first end parts,

wherein the semiconductor device further comprises a source contact line extending in the first direction to face the sidewall of the stack structure while being in direct contact with each of the first end parts.

10. The semiconductor device of claim 9, wherein the source contact line includes:

a doped silicon layer in direct contact with each of the first end parts, the doped silicon layer including a second conductivity type dopant different from the first conductivity type dopant;

a metal silicide layer disposed on the doped silicon layer; and

a metal layer disposed on the metal silicide layer.

11. The semiconductor device of claim 9, further comprising a spacer insulating layer disposed between the source contact line and the stack structure, the spacer insulating layer extending to cover the sidewall of each of the gate patterns.

12. The semiconductor device of claim 11, wherein the connection part extends to overlap the spacer insulating layer under the spacer insulating layer, and is opened toward the source contact line.

13. The semiconductor device of claim 9, further comprising a well contact line disposed under the source contact line, the well contact line electrically connecting the connection part and the well structure by penetrating a portion of the connection part extending along the top surface of the well structure.

14. The semiconductor device of claim 13, further comprising an inter-well-source insulating layer disposed between the source contact line and the well contact line.

15. The semiconductor device of claim 1, further comprising a multi-layered memory pattern extending along an outer surface of the channel pattern.

16. The semiconductor device of claim 1, further comprising a protective layer formed along at least one of the side and bottom surfaces of each of the gate patterns.

17. The semiconductor device of claim 1, wherein the gate patterns operate through capacitive coupling with a first horizontal conductive pattern adjacent to the gate patterns among the horizontal conductive patterns.

18. A semiconductor device comprising:

a well structure including a first conductivity type dopant;

stack structures disposed to be spaced apart from the well structure in a first direction, the stack structures being spaced apart from each other by a slit in a second direction, each stack structure including an end region adjacent to the slit and a central region extending from the end region;

a gate pattern overlapping with the end region of each of the stack structures under the end region, the gate pattern not overlapping with the central region;

a source contact line disposed in the slit, the source contact line further protruding toward the well structure than the gate pattern, the source contact line including a second conductivity type dopant;

a well contact line disposed under the source contact line, the well contact line being in contact with the well structure; and

a channel layer extending to a space between the well structure and the stack structures by penetrating the central region of each of the stack structures, the channel layer being penetrated by the source contact line and the well contact line.

19. The semiconductor device of claim 18, further comprising a source junction defined inside the channel layer adjacent to the source contact line, the source junction including the second conductivity type dopant.

20. A semiconductor device comprising:

a stack structure including horizontal conductive patterns and interlayer insulating layers, which are alternately stacked in a first direction;

a source contact line dividing the stack structure into a first and a second stack structure adjacent to each other in a second direction crossing the first direction;

a first gate pattern formed under the first stack structure to overlap in the first direction with an end region of the first stack structure which is adjacent to the source contact line wherein a width of the first gate pattern is smaller than that of the first stack structure in the second direction;

a second gate pattern formed under the second stack structure to overlap with an end region of the second stack structure which is adjacent to the source contact line, wherein a width of the second gate pattern is smaller than that of the second stack structure in the second direction; and

a channel pattern including vertical parts penetrating the stack structure, and a connection part disposed under the stack structure, the connection part connecting the vertical parts.