Redistribution layer for substrate contacts

• US 10,381,430 B2
• Filed: 01/08/2018
• Issued: 08/13/2019
• Est. Priority Date: 09/25/2014
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: X-Celeprint Limited
• Inventors: Bower, Christopher, Meitl, Matthew, Cok, Ronald S.
• Primary Examiner(s): Jang, Bo B
• Application Number:
  US15/864,898
• Publication Number:
  US 20180151664A1
• Time in Patent Office: 582 Days
• Field of Search: None
• CPC Class Codes: G06F 2203/04104 Multi-touch detection in digitiser, i.e. details about the simultaneous detection of a plurality of touching locations, e.g. multiple fingers or pen and finger
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/042 by opto-electronic means
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 27/156 two-dimensional arrays
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 2933/0075 relating to heat extraction or cooling elements
• CPC Class Codes: H01L 33/58 Optical field-shaping elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/64 Heat extraction or cooling elements
• CPC Class Codes: H10K 50/87 Arrangements for heating or cooling
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/179 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/18 Tiled displays
• CPC Class Codes: H10K 59/90 Assemblies of multiple devices comprising at least one organic light-emitting element
• CPC Class Codes: H10K 71/00 : Manufacture or treatment specially adapted for the organic devices covered by this subclass
• CPC Class Codes: H10K 71/80 : using temporary substrates

Abstract

A structure with an interconnection layer for redistribution of electrical connections includes a plurality of first electrical connections disposed on a substrate in a first arrangement. An insulating layer is disposed on the substrate over the first electrical connections. A plurality of second electrical connections is disposed on the insulating layer on a side of the insulating layer opposite the plurality of first electrical connections in a second arrangement. Each second electrical connection is electrically connected to a respective first electrical connection. An integrated circuit is disposed on the substrate and is electrically connected to the first electrical connections. The first electrical connections in the first arrangement have a greater spatial density than the second electrical connections in the second arrangement.

Claims

1. A method of making a display incorporating a structure with an interconnection layer for redistributing electrical connections, comprising:

providing a substrate having a side;

providing a plurality of first electrical connections disposed on the side of the substrate in a first arrangement, each of the plurality of first electrical connections having a first size;

disposing a single insulating layer comprising a cured material coated on the side of the substrate over the plurality of first electrical connections;

disposing a plurality of second electrical connections on the insulating layer in a second arrangement disposed on a side of the insulating layer opposite the plurality of first electrical connections, each of the plurality of second electrical connections having a second size, wherein the second sizes of the plurality of second electrical connections are greater than the first sizes of the plurality of first electrical connections, each second electrical connection of the plurality of second electrical connections electrically connected to a respective first electrical connection of the plurality of first electrical connections through a via having a via size corresponding to the first size of the respective first electrical connection and smaller than the second sizes of the plurality of second electrical connections; and

disposing one or more inorganic light emitters on the side of the substrate, the one or more inorganic light emitters electrically connected to the plurality of first electrical connections.

2. The method of claim 1, comprising assembling the substrate onto a backplane substrate.

3. The method of claim 1, comprising:

disposing one or more inorganic light emitters on each tile substrate of a plurality of tile substrates, the one or more inorganic light emitters on the tile substrate electrically connected to first tile electrical connections in a first tile arrangement disposed on the tile substrate;

forming a tile insulating layer disposed on each of the plurality of tile substrates over the first tile electrical connections;

forming a plurality of second tile electrical connections disposed on the tile insulating layer of each of the plurality of tile substrates in a second tile arrangement and disposed on a side of the tile insulating layer opposite the plurality of first tile electrical connections, each second tile electrical connection of the plurality of second tile electrical connections electrically connected to a respective connection of the first tile electrical connections disposed on the tile substrate, wherein the first tile electrical connections in the first tile arrangement on the tile substrate are more closely spaced than the second tile electrical connections in the second tile arrangement; and

assembling the plurality of tile substrates and the substrate onto a backplane substrate so that adjacent light emitters are spaced apart by a same distance.

4. The method of claim 1, wherein disposing the one or more inorganic light emitter(s) on the substrate comprises micro transfer printing the one or more inorganic light emitter(s) to the substrate.

5. The method of claim 1, wherein disposing the one or more inorganic light emitters comprises disposing a regular array of inorganic light emitters on the substrate, wherein each light emitter in the regular array is electrically connected to ones of the first electrical connections.

6. The method of claim 1, comprising disposing one or more integrated circuits on the side of the insulating layer opposite the plurality of first electrical connections and electrically connecting the one or more integrated circuits to one or more of the plurality of second electrical connections.

7. The method of claim 1, comprising providing a backplane substrate comprising backplane electrical connections, affixing the substrate to the backplane substrate, and electrically connecting the backplane electrical connections to the plurality of second electrical connections.

8. The method of claim 7, comprising providing one or more backplane integrated circuits, disposing the backplane integrated circuits on the backplane substrate, and electrically connecting the backplane integrated circuits to the backplane electrical connections.

9. The method of claim 8, comprising soldering the plurality of second electrical connections to the backplane electrical connections.

10. A display comprising:

a substrate having a side;

a plurality of first electrical connections disposed on the side of the substrate in a first arrangement, each of the plurality of first electrical connections having a first size;

a single insulating layer comprising a cured material coated on the side of the substrate over the plurality of first electrical connections;

a plurality of second electrical connections disposed on the insulating layer in a second arrangement on a side of the insulating layer opposite the plurality of first electrical connections, each of the plurality of second electrical connections having a second size, wherein the second sizes of the plurality of second electrical connections are greater than the first sizes of the plurality of first electrical connections, each second electrical connection of the plurality of second electrical connections electrically connected to a respective first electrical connection of the plurality of first electrical connections through a via having a via size corresponding to the first size of the respective first electrical connection and smaller than the second sizes of the plurality of second electrical connections; and

one or more inorganic light emitters on the side of the substrate, the one or more inorganic light emitters electrically connected to the plurality of first electrical connections.

11. The display of claim 10, comprising one or more integrated circuits disposed on a side of the insulating layer opposite the plurality of first electrical connections and electrically connected to one or more of the plurality of second electrical connections.

12. The display of claim 10, wherein the substrate is transparent and the one or more inorganic light emitters are disposed to emit light through the substrate.

13. The display of claim 10, comprising a backplane substrate comprising backplane electrical connections, wherein the substrate is assembled onto the backplane substrate and the backplane electrical connections are electrically connected to the plurality of second electrical connections.

14. The display of claim 13, wherein the plurality of second electrical connections are soldered to the backplane electrical connections.

15. The display of claim 13, comprising one or more backplane integrated circuits disposed on the backplane substrate, wherein the one or more backplane integrated circuits are electrically connected to one or more of the backplane electrical connections.

16. A display, comprising,

a backplane substrate comprising backplane electrical connections;

and

a plurality of tiles assembled on the backplane substrate, each of the plurality of tiles comprising

a tile substrate having a side;

a plurality of first electrical connections disposed on the side of the tile substrate in a first arrangement, each of the plurality of first electrical connections having a first size;

a single insulating layer comprising a cured material coated on the side of the tile substrate over the plurality of first electrical connections;

a plurality of second electrical connections disposed on the insulating layer in a second arrangement on a side of the insulating layer opposite the plurality of first electrical connections, each of the plurality of second electrical connections having a second size, wherein the second sizes of the plurality of second electrical connections are greater than the first sizes of the plurality of first electrical connections, each second electrical connection of the plurality of second electrical connections electrically connected to a respective first electrical connection of the plurality of first electrical connections through a via having a via size corresponding to the first size of the respective first electrical connection and smaller than the second sizes of the plurality of second electrical connections; and

one or more inorganic light emitters on the side of the tile substrate, the light emitters electrically connected to the plurality of first electrical connections,

wherein the backplane electrical connections are electrically connected to the plurality of second electrical connections of each of the tiles.

17. The display of claim 16, wherein the plurality of tiles comprises a first tile and a second tile, the tile substrate of each of the first tile and the second tile having an edge and wherein the edge of the tile substrate of the first tile is adjacent and substantially parallel to the edge of the tile substrate of the second tile.

18. The display of claim 17, wherein:

the first tile and the second tile each comprise an edge inorganic light emitter adjacent to the edge of the respective tile substrate and an interior inorganic light emitter that is not adjacent to the edge of the respective tile substrate,

wherein, for each of the first tile and the second tile, the edge inorganic light emitter and the interior inorganic light emitter are electrically connected to ones of the first electrical connections,

wherein the first electrical connections are spaced by a first spacing smaller than a second spacing of the second electrical connections, and

wherein a distance between the edge inorganic light emitter of the first tile and the edge inorganic light emitter of the second tile is substantially equal to (i) a distance between the edge inorganic light emitter and the interior edge inorganic light emitter of the first tile and (ii) a distance between the edge inorganic light emitter and the interior edge inorganic light emitter of the second tile.

19. The display of claim 18, wherein a plurality of edge inorganic light emitters and a plurality of interior inorganic light emitters are disposed on the tile substrate of each of the plurality of tiles and the plurality of edge inorganic light emitters and the plurality of interior inorganic light emitters form a regular array.

20. The display of claim 19, wherein the backplane substrate is a display substrate and the plurality of edge inorganic light emitters and the plurality of interior inorganic light emitters of each of the plurality of tiles together form a display.