Vertically stacked NFETS and PFETS with gate-all-around structure

• US 10,381,438 B2
• Filed: 11/02/2017
• Issued: 08/13/2019
• Est. Priority Date: 11/02/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Zhang, Jingyun, Ando, Takashi, Hashemi, Pouya, Lee, Choonghyun, Reznicek, Alexander
• Primary Examiner(s): Yushina, Galina G
• Application Number:
  US15/802,067
• Publication Number:
  US 20190131396A1
• Time in Patent Office: 649 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02112 characterised by the material of the layer
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 : oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 : and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/165 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41725 : Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 : using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78651 : Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor structure including vertically stacked nFETs and pFETs containing suspended semiconductor channel material nanosheets having an isolation layer located between a pFET S/D structure and an nFET S/D region is provided together with a method of forming such a structure. The pFET S/D structure includes a pFET S/D SiGe region having a first germanium content and an overlying SiGe region having a second germanium content that is greater than the first germanium content.

Claims

1. A semiconductor structure comprising:

a p-type field effect transistor (pFET) device comprising a first functional gate structure present on physically exposed surfaces, and between, each semiconductor channel material nanosheet of a first set of vertically stacked and suspended semiconductor channel material nanosheets, and a pFET source/drain (S/D) structure present on each side of the first set of vertically stacked and suspended semiconductor channel material nanosheets, wherein the pFET S/D structure comprises a stack of, and from bottom to top, a first SiGe region having a first germanium content and a second SiGe region having a second germanium content greater than the first germanium content;

an n-type field effect transistor (nFET) device stacked vertically above the pFET device and comprising a second functional gate structure present on physically exposed surfaces, and between, each semiconductor channel material nanosheet of a second set of vertically stacked and suspended semiconductor channel material nanosheets, and an nFET S/D region is present on each side of the second set of vertically stacked and suspended semiconductor channel material nanosheets and located above each pFET S/D structure;

a silicon dioxide layer present between the pFET S/D structure and the nFET S/D region, wherein the silicon dioxide layer has a topmost surface directly contacting a bottommost surface of the nFET S/D region, a bottommost surface directly contacting a topmost surface of the pFET S/D structure, and sidewalls that a vertically aligned with sidewalls of the pFET S/D structure and sidewalls of the nFET S/D region; and

a shared S/D contact structure located on a first side of the vertically stacked nFET and pFET device, wherein said shared S/D contact structure passes entirely through each of the nFET S/D region, the silicon dioxide layer and the second SiGe region of the pFET S/D structure, and only partially into the first SiGe region of the pFET S/D structure.

2. The semiconductor structure of claim 1, wherein each of the first and second functional gate structures comprises a same work function metal-containing material.

3. The semiconductor structure of claim 1, wherein the first functional gate structure comprises a p-type work function metal-containing material and the second functional gate structure comprises an n-type work function metal-containing material.

4. The semiconductor structure of claim 1, wherein sidewalls of the first and second functional gate structures contact sidewalls of an inner spacer.

5. The semiconductor structure of claim 1, further comprising a dielectric isolation layer located beneath the pFET device and on a surface of a semiconductor substrate.

6. The semiconductor structure of claim 1, wherein the first germanium content is from 50 atomic percent germanium to 60 atomic percent atomic percent germanium, and the second germanium content is from 55 atomic percent germanium to 75 atomic percent germanium.

7. The semiconductor structure of claim 1, wherein each semiconductor channel material nanosheet of the first and second sets of vertically stacked and suspended semiconductor channel material nanosheets is composed of a same semiconductor material.

8. The semiconductor structure of claim 7, wherein each semiconductor channel material nanosheet of the first and second sets of vertically stacked and suspended semiconductor channel material nanosheets is composed of silicon or a III-V compound semiconductor.

9. The semiconductor structure of claim 1, wherein the first SiGe region and the second SiGe region comprise silicon germanium and a p-type dopant.

10. The semiconductor structure of claim 1, further comprising an nFET S/D contact structure and a pFET S/D contact structure located on a second side of the vertically stacked nFET and pFET devices, opposite the first side, wherein the nFET S/D contact is present in the nFET S/D region and the pFET contact structure is present in the pFET S/D structure.

11. The semiconductor structure of claim 10, wherein the nFET S/D contact structure is separated from the pFET S/D contact structure by a dielectric material.