Interface engineering for high capacitance capacitor for liquid crystal display

• US 10,381,454 B2
• Filed: 01/20/2017
• Issued: 08/13/2019
• Est. Priority Date: 02/05/2016
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Patterson & Sheridan, LLP
• Inventors: Zhang, Xuena, Yim, Dong-Kil, Dai, Wenqing, You, Harvey, Won, Tae Kyung, Yang, Hsiao-Lin, Lin, Wan-Yu, Tsai, Yun-chu
• Primary Examiner(s): Yi, Changhyun
• Application Number:
  US15/411,724
• Publication Number:
  US 20170229490A1
• Time in Patent Office: 935 Days
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/02148 the material containing hafnium, e.g. HfSiOx or HfSiON
• CPC Class Codes: H01L 21/02159 the material containing zirconium, e.g. ZrSiOx
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02181 the material containing hafnium, e.g. HfO2
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02194 the material containing more than one metal element
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/4908 : for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H10K 59/1201 : Manufacture or treatment
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 : the pixel elements being capacitors
• CPC Class Codes: H10K 59/124 : Insulating layers formed between TFT elements and OLED elements

Abstract

Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.

Claims

1. A thin film transistor structure comprising:

a capacitor formed in a thin film transistor device, the capacitor further comprising;

a gate electrode disposed overlying a substrate;

a common electrode disposed overlying the gate electrode;

a dielectric layer formed on the common electrode, wherein the dielectric layer includes a bulk dielectric material sandwiched between a top interface protection layer and a bottom interface protection layer; and

a pixel electrode formed on the dielectric layer, the top interface protection layer formed in contact with the pixel electrode and the bottom interface protection layer formed in contact with the common electrode.

2. The structure of claim 1, wherein the dielectric layer is a high-k material having a dielectric constant greater than 8.

3. The structure of claim 2, wherein the top interface protection layer is a silicon oxide or silicon oxynitride layer.

4. The structure of claim 1, wherein the top interface protection layer is a silicon containing material.

5. The structure of claim 1, wherein the top interface protection layer is a silicon oxynitride layer when the dielectric layer is a silicon nitride layer.

6. The structure of claim 1, wherein the common electrode and the pixel electrode are fabricated from a material selected from a group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum (Al), tungsten (W), chromium (Cr), tantalum (Ta), titanium (Ti), molybdenum (Mo), magnesium (Mg), silver (Ag), gold (Au), chromium (Cr), silver nano ink, carbon nano tube (CNT), silver nano ink, graphene or alloys thereof.

7. The structure of claim 1, wherein the common electrode or the pixel electrode is a mesh or grid electrode.

8. The structure of claim 1, wherein the pixel electrode includes a first electrode and a second electrode disposed on the first electrode.

9. The structure of claim 8, wherein second electrode is a mesh or grid electrode.

10. A method for forming a capacitor structure on a substrate for thin film transistor applications comprising:

forming a gate electrode disposed overlying a substrate;

forming a common electrode disposed overlying the gate electrode;

forming a dielectric layer on the common electrode, wherein the dielectric layer includes a bulk dielectric material sandwiched between a top interface protection layer and a bottom interface protection layer; and

forming a pixel electrode on the dielectric layer, wherein the top interface protection layer is formed in contact with the pixel electrode and the bottom interface protection layer is formed in contact with the common electrode.

11. The method of claim 10, wherein the top interface protection layer is a silicon oxynitride layer or silicon oxide layer.

12. The method of claim 10, wherein the top interface protection layer is a silicon oxynitride layer when the dielectric layer is a silicon nitride layer.

13. The method of claim 10, wherein the top interface protection layer is a silicon oxide or silicon oxynitride layer when the dielectric layer is a high-k material having a dielectric constant greater than 8.

14. The method of claim 10, wherein the pixel electrode is a mesh or grid electrode.

15. The method of claim 10, wherein the common electrode and the pixel electrode are fabricated from a material selected from a group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum (Al), tungsten (W), chromium (Cr), tantalum (Ta), titanium (Ti), molybdenum (Mo), magnesium (Mg), silver (Ag), gold (Au), chromium (Cr), silver nano ink, carbon nano tube (CNT), silver nano ink, graphene or alloys thereof.

16. The method of claim 10, wherein the pixel electrode includes a first electrode and a second electrode disposed on the first electrode.

17. The method of claim 16, wherein the second electrode is a mesh or grid electrode.

18. A method for forming an insulating layer on a substrate for thin film transistor applications comprising:

forming a gate electrode disposed overlying the substrate;

forming a common electrode disposed overlying the gate electrode;

forming a high-k layer on the common electrode by an atomic layer deposition process or a hybrid process including atomic layer deposition and chemical vapor deposition process, wherein the high-k layer includes a bulk dielectric material sandwiched between a top interface protection layer and a bottom interface protection layer, wherein the high-k layer is one of a gate insulating layer, a passivation layer, a capacitor, an interlayer insulator, an etch stop layer in a thin film transistor device; and

forming a pixel electrode on the high-k layer, wherein the top interface protection layer is formed in contact with the pixel electrode and the bottom interface protection layer is formed in contact with the common electrode.

19. The method of claim 18, wherein the thin film transistor device is a low temperature polysilicon (LTPS) TFT device.