Interface engineering for high capacitance capacitor for liquid crystal display
First Claim
1. A thin film transistor structure comprising:
- a capacitor formed in a thin film transistor device, the capacitor further comprising;
a gate electrode disposed overlying a substrate;
a common electrode disposed overlying the gate electrode;
a dielectric layer formed on the common electrode, wherein the dielectric layer includes a bulk dielectric material sandwiched between a top interface protection layer and a bottom interface protection layer; and
a pixel electrode formed on the dielectric layer, the top interface protection layer formed in contact with the pixel electrode and the bottom interface protection layer formed in contact with the common electrode.
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Accused Products
Abstract
Embodiments of the disclosure generally provide methods of forming a capacitor with high capacitance and low leakage as well as a good interface control for thin film transistor (TFT) applications. In one embodiment, a thin film transistor structure includes a capacitor formed in a thin film transistor device. The capacitor further includes a common electrode disposed on a substrate, a dielectric layer formed on the common electrode and a pixel electrode formed on the dielectric layer. An interface protection layer formed between the common electrode and the dielectric layer, or between the dielectric layer and the pixel electrode. A gate insulating layer fabricated by a high-k material may also be utilized in the thin film transistor structure.
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Citations
19 Claims
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1. A thin film transistor structure comprising:
a capacitor formed in a thin film transistor device, the capacitor further comprising; a gate electrode disposed overlying a substrate; a common electrode disposed overlying the gate electrode; a dielectric layer formed on the common electrode, wherein the dielectric layer includes a bulk dielectric material sandwiched between a top interface protection layer and a bottom interface protection layer; and a pixel electrode formed on the dielectric layer, the top interface protection layer formed in contact with the pixel electrode and the bottom interface protection layer formed in contact with the common electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for forming a capacitor structure on a substrate for thin film transistor applications comprising:
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forming a gate electrode disposed overlying a substrate; forming a common electrode disposed overlying the gate electrode; forming a dielectric layer on the common electrode, wherein the dielectric layer includes a bulk dielectric material sandwiched between a top interface protection layer and a bottom interface protection layer; and forming a pixel electrode on the dielectric layer, wherein the top interface protection layer is formed in contact with the pixel electrode and the bottom interface protection layer is formed in contact with the common electrode. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A method for forming an insulating layer on a substrate for thin film transistor applications comprising:
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forming a gate electrode disposed overlying the substrate; forming a common electrode disposed overlying the gate electrode; forming a high-k layer on the common electrode by an atomic layer deposition process or a hybrid process including atomic layer deposition and chemical vapor deposition process, wherein the high-k layer includes a bulk dielectric material sandwiched between a top interface protection layer and a bottom interface protection layer, wherein the high-k layer is one of a gate insulating layer, a passivation layer, a capacitor, an interlayer insulator, an etch stop layer in a thin film transistor device; and forming a pixel electrode on the high-k layer, wherein the top interface protection layer is formed in contact with the pixel electrode and the bottom interface protection layer is formed in contact with the common electrode. - View Dependent Claims (19)
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Specification